Andreas Olofsson b9d3c5ac5c Verilator lint cleanup ...

~10 real bugs
-mostly name mismatches and bit range mistakes

2015-04-14 14:00:23 -04:00

..

dv

Changed to 20 bit address width for clarity in FPGA block

2014-11-05 19:37:25 -05:00

hdl

Verilator lint cleanup

2015-04-14 14:00:23 -04:00