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329 lines
14 KiB
XML
329 lines
14 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>adapteva.com</spirit:vendor>
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<spirit:library>Adapteva</spirit:library>
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<spirit:name>parallella_i2c</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>I2C</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="iic" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="iic_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>SCL_I</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>I2C_SCL_I</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>SCL_O</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>I2C_SCL_O</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>SCL_T</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>I2C_SCL_T</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>SDA_I</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>I2C_SDA_I</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>SDA_O</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>I2C_SDA_O</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>SDA_T</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>I2C_SDA_T</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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</spirit:busInterfaces>
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<spirit:model>
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<spirit:views>
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<spirit:view>
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<spirit:name>xilinx_verilogsynthesis</spirit:name>
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<spirit:displayName>Verilog Synthesis</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>parallella_i2c</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
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<spirit:displayName>Verilog Simulation</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>parallella_i2c</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_xpgui</spirit:name>
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<spirit:displayName>UI Layout</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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</spirit:view>
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</spirit:views>
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<spirit:ports>
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<spirit:port>
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<spirit:name>I2C_SDA_I</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="long" spirit:resolve="immediate">0</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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<spirit:vendorExtensions>
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<xilinx:portInfo>
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<xilinx:enablement>
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<xilinx:presence>required</xilinx:presence>
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</xilinx:enablement>
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</xilinx:portInfo>
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</spirit:vendorExtensions>
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</spirit:port>
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<spirit:port>
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<spirit:name>I2C_SCL_I</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="long" spirit:resolve="immediate">0</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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<spirit:vendorExtensions>
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<xilinx:portInfo>
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<xilinx:enablement>
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<xilinx:presence>required</xilinx:presence>
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</xilinx:enablement>
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</xilinx:portInfo>
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</spirit:vendorExtensions>
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</spirit:port>
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<spirit:port>
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<spirit:name>I2C_SDA</spirit:name>
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<spirit:wire>
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<spirit:direction>inout</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="long" spirit:resolve="immediate">0</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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<spirit:vendorExtensions>
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<xilinx:portInfo>
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<xilinx:enablement>
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<xilinx:presence>required</xilinx:presence>
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</xilinx:enablement>
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</xilinx:portInfo>
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</spirit:vendorExtensions>
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</spirit:port>
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<spirit:port>
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<spirit:name>I2C_SCL</spirit:name>
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<spirit:wire>
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<spirit:direction>inout</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="long" spirit:resolve="immediate">0</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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<spirit:vendorExtensions>
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<xilinx:portInfo>
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<xilinx:enablement>
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<xilinx:presence>required</xilinx:presence>
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</xilinx:enablement>
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</xilinx:portInfo>
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</spirit:vendorExtensions>
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</spirit:port>
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<spirit:port>
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<spirit:name>I2C_SDA_O</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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<spirit:vendorExtensions>
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<xilinx:portInfo>
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<xilinx:enablement>
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<xilinx:presence>required</xilinx:presence>
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</xilinx:enablement>
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</xilinx:portInfo>
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</spirit:vendorExtensions>
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</spirit:port>
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<spirit:port>
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<spirit:name>I2C_SDA_T</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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<spirit:vendorExtensions>
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<xilinx:portInfo>
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<xilinx:enablement>
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<xilinx:presence>required</xilinx:presence>
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</xilinx:enablement>
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</xilinx:portInfo>
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</spirit:vendorExtensions>
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</spirit:port>
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<spirit:port>
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<spirit:name>I2C_SCL_O</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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<spirit:vendorExtensions>
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<xilinx:portInfo>
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<xilinx:enablement>
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<xilinx:presence>required</xilinx:presence>
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</xilinx:enablement>
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</xilinx:portInfo>
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</spirit:vendorExtensions>
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</spirit:port>
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<spirit:port>
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<spirit:name>I2C_SCL_T</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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<spirit:vendorExtensions>
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<xilinx:portInfo>
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<xilinx:enablement>
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<xilinx:presence>required</xilinx:presence>
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</xilinx:enablement>
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</xilinx:portInfo>
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</spirit:vendorExtensions>
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</spirit:port>
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</spirit:ports>
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</spirit:model>
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<spirit:fileSets>
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<spirit:fileSet>
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<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>hdl/parallella_i2c.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_53deb422</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>hdl/parallella_i2c.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>xgui/parallella_i2c_v1_0.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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<spirit:userFileType>CHECKSUM_e65e5adf</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
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</spirit:fileSets>
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<spirit:description>I2C Open-Drain Implementation</spirit:description>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>Component_Name</spirit:name>
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<spirit:displayName>Component Name</spirit:displayName>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">parallella_i2c_v1_0</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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<spirit:vendorExtensions>
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<xilinx:coreExtensions>
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<xilinx:supportedFamilies>
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<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
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<xilinx:taxonomy>/Adapteva</xilinx:taxonomy>
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</xilinx:taxonomies>
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<xilinx:displayName>parallella_i2c_v1_0</xilinx:displayName>
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<xilinx:vendorDisplayName>Adapteva, Inc.</xilinx:vendorDisplayName>
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<xilinx:vendorURL>http://www.adapteva.com</xilinx:vendorURL>
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<xilinx:coreRevision>2</xilinx:coreRevision>
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<xilinx:coreCreationDateTime>2015-01-13T18:14:34Z</xilinx:coreCreationDateTime>
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<xilinx:tags>
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<xilinx:tag xilinx:name="user.org:user:parallella_i2c:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/i2c</xilinx:tag>
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<xilinx:tag xilinx:name="adapteva.com:user:parallella_i2c:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/i2c</xilinx:tag>
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<xilinx:tag xilinx:name="adapteva.com:Adapteva:parallella_i2c:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/i2c</xilinx:tag>
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</xilinx:tags>
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</xilinx:coreExtensions>
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<xilinx:packagingInfo>
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<xilinx:xilinxVersion>2014.3</xilinx:xilinxVersion>
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</xilinx:packagingInfo>
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</spirit:vendorExtensions>
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</spirit:component>
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