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oh/elink/dv/build_eref.sh
Andreas Olofsson 8915fd6dfd Adding environment for chip reference model
- Turns out I had a nasty bug that was masked by using my own RX to loopback the TX. Since the new RX is very benign with a  programmable fifo full flag the timing is quite relaxed.
- The legacy elink for e16 has a strict wait policy. When wait is raised high, you must stop pretty much immediately.
- I struggled with testing this bug on the parallella for 2 days.
- Putting together the test environment uncovered the bug in a couple of hours. F**K, I should know better!!
2015-11-24 01:07:49 -05:00

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#!/bin/bash
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dut="e16ref"
top="../../common/dv/dv_top.v"
iverilog -g2005 -DTARGET_SIM=1 -DTARGET_XILINX=1 elink_e16_model.v $top dut_${dut}.v -f ../../common/dv/libs.cmd -o ${dut}.vvp
#-pfileline=1
#-Wall