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33 lines
962 B
Verilog
33 lines
962 B
Verilog
module packet2emesh(/*AUTOARG*/
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// Outputs
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write_out, datamode_out, ctrlmode_out, data_out, dstaddr_out,
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srcaddr_out,
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// Inputs
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packet_in
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);
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parameter PW = 104; //packet width
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parameter DW = 32; //data width
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parameter AW = 32; //addess width
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//Input packet
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input [PW-1:0] packet_in;
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//Emesh signal bundle
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output write_out;
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output [1:0] datamode_out;
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output [3:0] ctrlmode_out;
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output [DW-1:0] data_out; //TODO: fix to make relative to PW
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output [AW-1:0] dstaddr_out;
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output [AW-1:0] srcaddr_out;
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assign write_out = packet_in[0];
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assign datamode_out[1:0] = packet_in[2:1];
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assign ctrlmode_out[3:0] = packet_in[6:3];
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assign dstaddr_out[31:0] = packet_in[39:8];
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assign srcaddr_out[31:0] = packet_in[103:72];
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assign data_out[31:0] = packet_in[71:40];
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endmodule // packet2emesh
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