mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
73229ff914
-adding clock bypass mode for esystx[12] -removing monitor feature on erx -remove loopback support from doc -add clock bypass mode for esysclk -shortening register names (descriptive enough) -added debug signal information -moving registers to elink -making elink version programmable (to support plug in boards) -reorganized debug signals and added stickys -added timeout for axi slave -removed embox status bit (redudant, don't poll status) -renamed EMBOX0-->EMBOXLO -moved datain interface straight to ecfg (cleanup) -changed etx arbiter priority to increase stability -created the esaxi_mux block -fixed some missing ports issues in stubs Now comes the fun part...verification... Andreas
175 lines
6.1 KiB
Verilog
175 lines
6.1 KiB
Verilog
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`timescale 1 ns / 1 ps
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module esaxi #
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(
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// Users to add parameters here
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parameter [11:0] C_READ_TAG_ADDR = 12'h810,
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// User parameters ends
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// Do not modify the parameters beyond this line
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// Parameters of Axi Slave Bus Interface S00_AXI
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parameter integer C_S00_AXI_ID_WIDTH = 12,
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parameter integer C_S00_AXI_DATA_WIDTH = 32,
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parameter integer C_S00_AXI_ADDR_WIDTH = 30,
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parameter integer C_S00_AXI_AWUSER_WIDTH = 0,
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parameter integer C_S00_AXI_ARUSER_WIDTH = 0,
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parameter integer C_S00_AXI_WUSER_WIDTH = 0,
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parameter integer C_S00_AXI_RUSER_WIDTH = 0,
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parameter integer C_S00_AXI_BUSER_WIDTH = 0
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)
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(
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// FIFO write port, write requests
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output wire [102:0] emwr_wr_data,
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output wire emwr_wr_en,
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input wire emwr_full,
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input wire emwr_prog_full,
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// FIFO write port, read requests
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output wire [102:0] emrq_wr_data,
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output wire emrq_wr_en,
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input wire emrq_full,
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input wire emrq_prog_full,
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// FIFO read port, read responses
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input wire [102:0] emrr_rd_data,
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output wire emrr_rd_en,
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input wire emrr_empty,
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// Control bits from eConfig
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input [3:0] ecfg_tx_ctrlmode,
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input [11:0] ecfg_coreid,
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input ecfg_axi_timeout_enable,
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// User ports endsx
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// Do not modify the ports beyond this line
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// Ports of Axi Slave Bus Interface S00_AXI
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input wire s00_axi_aclk,
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input wire s00_axi_aresetn,
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input wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_awid,
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input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
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input wire [7 : 0] s00_axi_awlen,
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input wire [2 : 0] s00_axi_awsize,
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input wire [1 : 0] s00_axi_awburst,
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input wire s00_axi_awlock,
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input wire [3 : 0] s00_axi_awcache,
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input wire [2 : 0] s00_axi_awprot,
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input wire [3 : 0] s00_axi_awqos,
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input wire [3 : 0] s00_axi_awregion,
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input wire [C_S00_AXI_AWUSER_WIDTH-1 : 0] s00_axi_awuser,
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input wire s00_axi_awvalid,
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output wire s00_axi_awready,
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input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
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input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
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input wire s00_axi_wlast,
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input wire [C_S00_AXI_WUSER_WIDTH-1 : 0] s00_axi_wuser,
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input wire s00_axi_wvalid,
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output wire s00_axi_wready,
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output wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_bid,
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output wire [1 : 0] s00_axi_bresp,
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output wire [C_S00_AXI_BUSER_WIDTH-1 : 0] s00_axi_buser,
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output wire s00_axi_bvalid,
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input wire s00_axi_bready,
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input wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_arid,
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input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
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input wire [7 : 0] s00_axi_arlen,
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input wire [2 : 0] s00_axi_arsize,
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input wire [1 : 0] s00_axi_arburst,
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input wire s00_axi_arlock,
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input wire [3 : 0] s00_axi_arcache,
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input wire [2 : 0] s00_axi_arprot,
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input wire [3 : 0] s00_axi_arqos,
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input wire [3 : 0] s00_axi_arregion,
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input wire [C_S00_AXI_ARUSER_WIDTH-1 : 0] s00_axi_aruser,
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input wire s00_axi_arvalid,
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output wire s00_axi_arready,
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output wire [C_S00_AXI_ID_WIDTH-1 : 0] s00_axi_rid,
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output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
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output wire [1 : 0] s00_axi_rresp,
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output wire s00_axi_rlast,
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output wire [C_S00_AXI_RUSER_WIDTH-1 : 0] s00_axi_ruser,
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output wire s00_axi_rvalid,
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input wire s00_axi_rready
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);
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// Instantiation of Axi Bus Interface S00_AXI
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esaxi_logic # (
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.C_READ_TAG_ADDR(C_READ_TAG_ADDR),
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.C_S_AXI_ID_WIDTH(C_S00_AXI_ID_WIDTH),
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.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
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.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH),
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.C_S_AXI_AWUSER_WIDTH(C_S00_AXI_AWUSER_WIDTH),
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.C_S_AXI_ARUSER_WIDTH(C_S00_AXI_ARUSER_WIDTH),
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.C_S_AXI_WUSER_WIDTH(C_S00_AXI_WUSER_WIDTH),
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.C_S_AXI_RUSER_WIDTH(C_S00_AXI_RUSER_WIDTH),
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.C_S_AXI_BUSER_WIDTH(C_S00_AXI_BUSER_WIDTH)
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) esaxi_logic (
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.emwr_wr_data (emwr_wr_data),
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.emwr_wr_en (emwr_wr_en),
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.emwr_full (emwr_full),
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.emwr_prog_full (emwr_prog_full),
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.emrq_wr_data (emrq_wr_data),
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.emrq_wr_en (emrq_wr_en),
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.emrq_full (emrq_full),
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.emrq_prog_full (emrq_prog_full),
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.emrr_rd_data (emrr_rd_data),
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.emrr_rd_en (emrr_rd_en),
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.emrr_empty (emrr_empty),
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.ecfg_tx_ctrl_mode (ecfg_tx_ctrlmode),
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.ecfg_coreid (ecfg_coreid),
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.S_AXI_ACLK(s00_axi_aclk),
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.S_AXI_ARESETN(s00_axi_aresetn),
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.S_AXI_AWID(s00_axi_awid),
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.S_AXI_AWADDR(s00_axi_awaddr),
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.S_AXI_AWLEN(s00_axi_awlen),
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.S_AXI_AWSIZE(s00_axi_awsize),
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.S_AXI_AWBURST(s00_axi_awburst),
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.S_AXI_AWLOCK(s00_axi_awlock),
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.S_AXI_AWCACHE(s00_axi_awcache),
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.S_AXI_AWPROT(s00_axi_awprot),
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.S_AXI_AWQOS(s00_axi_awqos),
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.S_AXI_AWREGION(s00_axi_awregion),
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.S_AXI_AWUSER(s00_axi_awuser),
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.S_AXI_AWVALID(s00_axi_awvalid),
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.S_AXI_AWREADY(s00_axi_awready),
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.S_AXI_WDATA(s00_axi_wdata),
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.S_AXI_WSTRB(s00_axi_wstrb),
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.S_AXI_WLAST(s00_axi_wlast),
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.S_AXI_WUSER(s00_axi_wuser),
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.S_AXI_WVALID(s00_axi_wvalid),
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.S_AXI_WREADY(s00_axi_wready),
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.S_AXI_BID(s00_axi_bid),
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.S_AXI_BRESP(s00_axi_bresp),
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.S_AXI_BUSER(s00_axi_buser),
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.S_AXI_BVALID(s00_axi_bvalid),
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.S_AXI_BREADY(s00_axi_bready),
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.S_AXI_ARID(s00_axi_arid),
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.S_AXI_ARADDR(s00_axi_araddr),
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.S_AXI_ARLEN(s00_axi_arlen),
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.S_AXI_ARSIZE(s00_axi_arsize),
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.S_AXI_ARBURST(s00_axi_arburst),
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.S_AXI_ARLOCK(s00_axi_arlock),
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.S_AXI_ARCACHE(s00_axi_arcache),
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.S_AXI_ARPROT(s00_axi_arprot),
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.S_AXI_ARQOS(s00_axi_arqos),
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.S_AXI_ARREGION(s00_axi_arregion),
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.S_AXI_ARUSER(s00_axi_aruser),
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.S_AXI_ARVALID(s00_axi_arvalid),
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.S_AXI_ARREADY(s00_axi_arready),
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.S_AXI_RID(s00_axi_rid),
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.S_AXI_RDATA(s00_axi_rdata),
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.S_AXI_RRESP(s00_axi_rresp),
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.S_AXI_RLAST(s00_axi_rlast),
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.S_AXI_RUSER(s00_axi_ruser),
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.S_AXI_RVALID(s00_axi_rvalid),
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.S_AXI_RREADY(s00_axi_rready)
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);
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// Add user logic here
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// User logic ends
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endmodule
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