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-Each directory contains one sub block -Each directory contains a dv/docs/hdl directory, self contained. -May need to add constraints directory as well at some point. -This is the right thing to do, make each block modular and self contained.
177 lines
6.7 KiB
Verilog
177 lines
6.7 KiB
Verilog
/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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/*###########################################################################
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# Function: AXI slave wrapper for mailbox FIFO
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#
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############################################################################
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*/
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module axi_embox (/*AUTOARG*/
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// Outputs
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s_axi_awready, s_axi_wready, s_axi_bresp, s_axi_bvalid,
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s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid,
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embox_full, embox_empty,
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// Inputs
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s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awlen, s_axi_awsize,
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s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
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s_axi_awvalid, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid,
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s_axi_bready, s_axi_araddr, s_axi_arlen, s_axi_arsize,
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s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot,
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s_axi_arvalid, s_axi_rready
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);
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parameter AW = 32; //axi addr width
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parameter DW = 32; //axi data width
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parameter SW = 4; //==ADW/8
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parameter MAW = 6; //memory side address width
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/*****************************/
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/*AXI SLAVE INTERFACE */
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/*****************************/
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//Global signals
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input s_axi_aclk; //clock source for axi slave interfaces
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input s_axi_aresetn; //asynchronous reset signal, active low
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//Write address channel
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input [AW-1:0] s_axi_awaddr; //write address
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input [3:0] s_axi_awlen; //burst length (number of data transfers)
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input [2:0] s_axi_awsize; //burst size (size of each transfer)
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input [1:0] s_axi_awburst; //burst type
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input [1:0] s_axi_awlock; //lock type (atomic characteristics)
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input [3:0] s_axi_awcache; //memory type
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input [2:0] s_axi_awprot; //protection type
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input s_axi_awvalid; //write address valid
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output s_axi_awready; //write address ready
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//Write data channel
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input [DW-1:0] s_axi_wdata; //write data
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input [SW-1:0] s_axi_wstrb; //write strobes
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input s_axi_wlast; //indicats last write transfer in burst
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input s_axi_wvalid; //write valid
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output s_axi_wready; //write channel ready
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//Buffered write response channel
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input s_axi_bready; //write ready
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output [1:0] s_axi_bresp; //write response
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output s_axi_bvalid; //write response valid
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//Read address channel
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input [AW-1:0] s_axi_araddr; //read address
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input [3:0] s_axi_arlen; //burst lenght (number of data transfers)
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input [2:0] s_axi_arsize; //burst size (size of each transfer)
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input [1:0] s_axi_arburst; //burst type
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input [1:0] s_axi_arlock; //lock type (atomic characteristics)
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input [3:0] s_axi_arcache; //memory type
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input [2:0] s_axi_arprot; //protection type
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input s_axi_arvalid; //read address valid
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output s_axi_arready; //read address ready
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//Read data channel
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output [DW-1:0] s_axi_rdata; //read data
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output [1:0] s_axi_rresp; //read response
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output s_axi_rlast; //indicates last read transfer in burst
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output s_axi_rvalid; //read valid
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input s_axi_rready; //read ready
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/*****************************/
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/*MAILBOX OUTPUTS */
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/*****************************/
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output embox_full;
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output embox_empty;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire mi_access; // From axi_memif of axi_memif.v
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wire [MAW-1:0] mi_addr; // From axi_memif of axi_memif.v
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wire [DW-1:0] mi_data_in; // From axi_memif of axi_memif.v
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wire mi_write; // From axi_memif of axi_memif.v
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// End of automatics
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [DW-1:0] mi_data_out; // From embox of embox.v
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/*****************************/
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/*AXI INSTANCE */
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/*****************************/
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axi_memif axi_memif(/*AUTOINST*/
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// Outputs
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.s_axi_awready (s_axi_awready),
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.s_axi_wready (s_axi_wready),
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.s_axi_bresp (s_axi_bresp[1:0]),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_arready (s_axi_arready),
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.s_axi_rdata (s_axi_rdata[DW-1:0]),
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.s_axi_rresp (s_axi_rresp[1:0]),
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.s_axi_rlast (s_axi_rlast),
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.s_axi_rvalid (s_axi_rvalid),
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.mi_addr (mi_addr[MAW-1:0]),
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.mi_access (mi_access),
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.mi_write (mi_write),
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.mi_data_in (mi_data_in[DW-1:0]),
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// Inputs
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_awaddr (s_axi_awaddr[AW-1:0]),
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.s_axi_awlen (s_axi_awlen[3:0]),
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.s_axi_awsize (s_axi_awsize[2:0]),
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.s_axi_awburst (s_axi_awburst[1:0]),
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.s_axi_awlock (s_axi_awlock[1:0]),
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.s_axi_awcache (s_axi_awcache[3:0]),
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.s_axi_awprot (s_axi_awprot[2:0]),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_wdata (s_axi_wdata[DW-1:0]),
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.s_axi_wstrb (s_axi_wstrb[SW-1:0]),
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.s_axi_wlast (s_axi_wlast),
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.s_axi_wvalid (s_axi_wvalid),
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.s_axi_bready (s_axi_bready),
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.s_axi_araddr (s_axi_araddr[AW-1:0]),
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.s_axi_arlen (s_axi_arlen[3:0]),
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.s_axi_arsize (s_axi_arsize[2:0]),
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.s_axi_arburst (s_axi_arburst[1:0]),
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.s_axi_arlock (s_axi_arlock[1:0]),
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.s_axi_arcache (s_axi_arcache[3:0]),
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.s_axi_arprot (s_axi_arprot[2:0]),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_rready (s_axi_rready),
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.mi_data_out (mi_data_out[DW-1:0]));
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/*****************************/
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/*EMBOX INSTANCE */
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/*****************************/
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embox embox (.mi_addr (mi_addr[5:0]),
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/*AUTOINST*/
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// Outputs
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.mi_data_out (mi_data_out[DW-1:0]),
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.embox_full (embox_full),
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.embox_empty (embox_empty),
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// Inputs
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.reset (reset),
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.clk (clk),
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.mi_access (mi_access),
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.mi_write (mi_write),
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.mi_data_in (mi_data_in[DW-1:0]));
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endmodule // emmu
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// Local Variables:
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// verilog-library-directories:("." "../axi")
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// End:
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