Andreas Olofsson 73229ff914 Major cleanup, refactoring, and feature completion ...

-adding clock bypass mode for esystx[12]
-removing monitor feature on erx
-remove loopback support from doc
-add clock bypass mode for esysclk
-shortening register names (descriptive enough)
-added debug signal information
-moving registers to elink
-making elink version programmable (to support plug in boards)
-reorganized debug signals and added stickys
-added timeout for axi slave
-removed embox status bit (redudant, don't poll status)
-renamed EMBOX0-->EMBOXLO
-moved datain interface straight to ecfg (cleanup)
-changed etx arbiter priority to increase stability
-created the esaxi_mux block
-fixed some missing ports issues in stubs

Now comes the fun part...verification...
Andreas

2015-04-11 00:04:18 -04:00

..

dv

emmu: Refactor and add verilator testbench

2015-04-10 15:30:54 +02:00

hdl

Major cleanup, refactoring, and feature completion

2015-04-11 00:04:18 -04:00