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63 lines
1.8 KiB
Verilog
63 lines
1.8 KiB
Verilog
module memory_writemask(/*AUTOARG*/
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// Outputs
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we,
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// Inputs
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write, datamode, addr
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);
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input write;
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input [1:0] datamode;
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input [2:0] addr;
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output [7:0] we;
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reg [7:0] we;
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//Write mask
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always@*
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casez({write, datamode[1:0],addr[2:0]})
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//Byte
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6'b100000 : we[7:0] = 8'b00000001;
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6'b100001 : we[7:0] = 8'b00000010;
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6'b100010 : we[7:0] = 8'b00000100;
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6'b100011 : we[7:0] = 8'b00001000;
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6'b100100 : we[7:0] = 8'b00010000;
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6'b100101 : we[7:0] = 8'b00100000;
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6'b100110 : we[7:0] = 8'b01000000;
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6'b100111 : we[7:0] = 8'b10000000;
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//Short
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6'b10100? : we[7:0] = 8'b00000011;
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6'b10101? : we[7:0] = 8'b00001100;
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6'b10110? : we[7:0] = 8'b00110000;
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6'b10111? : we[7:0] = 8'b11000000;
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//Word
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6'b1100?? : we[7:0] = 8'b00001111;
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6'b1101?? : we[7:0] = 8'b11110000;
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//Double
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6'b111??? : we[7:0] = 8'b11111111;
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default : we[7:0] = 8'b00000000;
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endcase // casez ({write, datamode[1:0],addr[2:0]})
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endmodule // memory_writemask
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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