Ola Jeppsson 755904486e parallella/fpga: Rename headless to headless_e16_z7020 ...

Modify build script to output:
parallella_e16_headless_gpiose_7020.bit.bin

This is the same naming convention used by the old elink code.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>

2016-03-11 16:31:18 +01:00

..

dv

Fixing synchronization reset speed path

2015-11-09 00:16:35 -05:00

fpga

parallella/fpga: Rename headless to headless_e16_z7020

2016-03-11 16:31:18 +01:00

hdl

parallella/hdl/parallella_base:pgpio: Inherit NGPIO

2016-03-11 16:23:46 +01:00