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40 lines
1.0 KiB
Verilog
40 lines
1.0 KiB
Verilog
module spi_io(/*AUTOARG*/
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// Outputs
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ss_sel,
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// Inouts
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sclk, mosi, miso, ss
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);
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//##############################################################
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//#INTERFACE
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//###############################################################
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parameter N = 1; // number of slave selects supported
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//SPI IO interface
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inout sclk; // serial clk
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inout mosi; // master output / slave input
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inout miso; // master input / slave output
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inout ss; // primary slave select master/slave
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output [N-2:0] ss_sel; // extra slave selects in master mode
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//master side
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input m_mclk; //master clock
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input m_mosi; //master output
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input [N-1:0] m_ss; //slave select
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output m_miso; //master input
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//slave side
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output s_mclk; //slave clock
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output s_mosi; //slave input
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output s_ss; //slave select
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input s_miso; //slave output
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//place IO buffers
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endmodule // spi_io
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