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18 lines
216 B
Verilog
18 lines
216 B
Verilog
module IBUFDS (/*AUTOARG*/
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// Outputs
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O,
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// Inputs
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I, IB
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);
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parameter DIFF_TERM=0;
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parameter IOSTANDARD=0;
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input I;
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input IB;
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output O;
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assign O = I & ~IB;
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endmodule // IBUFDS
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