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504 lines
16 KiB
Verilog
504 lines
16 KiB
Verilog
module esaxi (/*autoarg*/
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// Outputs
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txwr_access, txwr_packet, txrd_access, txrd_packet, rxrr_wait,
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s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
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s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp, s_axi_rvalid,
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s_axi_wready,
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// Inputs
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txwr_wait, txrd_wait, rxrr_access, rxrr_packet, s_axi_aclk,
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s_axi_aresetn, s_axi_arid, s_axi_araddr, s_axi_arburst,
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s_axi_arcache, s_axi_arlock, s_axi_arlen, s_axi_arprot,
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s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid, s_axi_awaddr,
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s_axi_awburst, s_axi_awcache, s_axi_awlock, s_axi_awlen,
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s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
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s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast,
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s_axi_wstrb, s_axi_wvalid
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);
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parameter [11:0] ID = 12'h810;
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parameter IDW = 12;
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parameter PW = 104;
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parameter [15:0] RETURN_ADDR = {ID,4'hE};
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parameter AW = 32;
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parameter DW = 32;
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/*****************************/
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/*Write request for TX fifo */
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/*****************************/
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output txwr_access;
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output [PW-1:0] txwr_packet;
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input txwr_wait;
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/*****************************/
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/*Read request for TX fifo */
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/*****************************/
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output txrd_access;
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output [PW-1:0] txrd_packet;
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input txrd_wait;
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/*****************************/
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/*Read response from RX fifo */
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/*****************************/
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input rxrr_access;
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input [PW-1:0] rxrr_packet;
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output rxrr_wait;
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/*****************************/
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/*AXI slave interface */
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/*****************************/
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//Clock and reset
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input s_axi_aclk;
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input s_axi_aresetn;
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//Read address channel
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input [IDW-1:0] s_axi_arid; //write address ID
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input [31:0] s_axi_araddr;
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input [1:0] s_axi_arburst;
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input [3:0] s_axi_arcache;
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input [1:0] s_axi_arlock;
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input [7:0] s_axi_arlen;
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input [2:0] s_axi_arprot;
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input [3:0] s_axi_arqos;
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output s_axi_arready;
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input [2:0] s_axi_arsize;
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input s_axi_arvalid;
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//Write address channel
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input [IDW-1:0] s_axi_awid; //write address ID
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input [31:0] s_axi_awaddr;
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input [1:0] s_axi_awburst;
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input [3:0] s_axi_awcache;
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input [1:0] s_axi_awlock;
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input [7:0] s_axi_awlen;
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input [2:0] s_axi_awprot;
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input [3:0] s_axi_awqos;
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input [2:0] s_axi_awsize;
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input s_axi_awvalid;
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output s_axi_awready;
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//Buffered write response channel
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output [IDW-1:0] s_axi_bid; //write address ID
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output [1:0] s_axi_bresp;
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output s_axi_bvalid;
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input s_axi_bready;
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//Read channel
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output [IDW-1:0] s_axi_rid; //write address ID
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output [31:0] s_axi_rdata;
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output s_axi_rlast;
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output [1:0] s_axi_rresp;
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output s_axi_rvalid;
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input s_axi_rready;
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//Write channel
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input [IDW-1:0] s_axi_wid; //write address ID
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input [31:0] s_axi_wdata;
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input s_axi_wlast;
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input [3:0] s_axi_wstrb;
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input s_axi_wvalid;
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output s_axi_wready;
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//###################################################
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//#WIRE/REG DECLARATIONS
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//###################################################
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reg s_axi_awready;
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reg s_axi_wready;
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reg s_axi_bvalid;
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reg [1:0] s_axi_bresp;
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reg s_axi_arready;
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reg [31:0] axi_awaddr; // 32b for epiphany addr
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reg [1:0] axi_awburst;
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reg [2:0] axi_awsize;
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reg [31:0] axi_araddr;
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reg [7:0] axi_arlen;
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reg [1:0] axi_arburst;
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reg [2:0] axi_arsize;
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reg [31:0] s_axi_rdata;
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reg [1:0] s_axi_rresp;
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reg s_axi_rlast;
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reg s_axi_rvalid;
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reg read_active;
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reg [31:0] read_addr;
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reg write_active;
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reg b_wait; // waiting to issue write response (unlikely?)
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reg txwr_access;
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reg [1:0] txwr_datamode;
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reg [31:0] txwr_dstaddr;
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reg [31:0] txwr_data;
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reg [31:0] txwr_data_reg;
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reg [31:0] txwr_dstaddr_reg;
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reg [1:0] txwr_datamode_reg;
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reg txrd_access;
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reg [1:0] txrd_datamode;
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reg [31:0] txrd_dstaddr;
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reg [31:0] txrd_srcaddr; //read reaspne address
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reg pre_wr_en; // delay for data alignment
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reg ractive_reg; // need leading edge of active for 1st req
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reg rnext;
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wire last_wr_beat;
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wire last_rd_beat;
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wire [31:0] rxrr_mux_data;
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wire [DW-1:0] rxrr_data;
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//###################################################
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//#PACKET TO MESH
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//###################################################
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//TXWR
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emesh2packet e2p_txwr (
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// Outputs
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.packet_out (txwr_packet[PW-1:0]),
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// Inputs
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.access_in (txwr_access),
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.write_in (1'b1),
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.datamode_in (txwr_datamode[1:0]),
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.ctrlmode_in (4'b0),
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.dstaddr_in (txwr_dstaddr[AW-1:0]),
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.data_in (txwr_data[DW-1:0]),
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.srcaddr_in (32'b0)//only 32b slave write supported
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);
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//TXRD
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emesh2packet e2p_txrd (
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// Outputs
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.packet_out (txrd_packet[PW-1:0]),
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// Inputs
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.access_in (txrd_access),
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.write_in (txrd_write),
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.datamode_in (txrd_datamode[1:0]),
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.ctrlmode_in (4'b0),
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.dstaddr_in (txrd_dstaddr[AW-1:0]),
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.data_in (32'b0),
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.srcaddr_in (txrd_srcaddr[AW-1:0])
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);
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//RXRR
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packet2emesh p2e_rxrr (
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// Outputs
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.access_out (),
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.write_out (),
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.datamode_out (),
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.ctrlmode_out (),
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.dstaddr_out (),
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.data_out (rxrr_data[DW-1:0]),
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.srcaddr_out (),
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// Inputs
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.packet_in (rxrr_packet[PW-1:0])
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);
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//###################################################
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//#WRITE ADDRESS CHANNEL
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//###################################################
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assign last_wr_beat = s_axi_wready & s_axi_wvalid & s_axi_wlast;
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// axi_awready is asserted when there is no write transfer in progress
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always @(posedge s_axi_aclk )
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begin
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if(~s_axi_aresetn)
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begin
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s_axi_awready <= 1'b0;
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write_active <= 1'b0;
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end
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else
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begin
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// we're always ready for an address cycle if we're not doing something else
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// note: might make this faster by going ready on last beat instead of after,
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// but if we want the very best each channel should be fifo'd.
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if( ~s_axi_awready & ~write_active & ~b_wait )
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s_axi_awready <= 1'b1;
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else if( s_axi_awvalid )
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s_axi_awready <= 1'b0;
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// the write cycle is "active" as soon as we capture an address, it
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// ends on the last beat.
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if( s_axi_awready & s_axi_awvalid )
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write_active <= 1'b1;
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else if( last_wr_beat )
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write_active <= 1'b0;
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end // else: !if(~s_axi_aresetn)
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end // always @ (posedge s_axi_aclk )
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// capture address & other aw info, update address during cycle
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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//s_axi_bid <= 'd0; // capture for write response
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axi_awaddr[31:0] <= 32'd0;
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axi_awsize[2:0] <= 3'd0;
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axi_awburst[1:0] <= 2'd0;
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end
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else
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begin
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if( s_axi_awready & s_axi_awvalid )
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begin
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axi_awaddr[31:0] <= s_axi_awaddr[31:0];
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axi_awsize <= s_axi_awsize; // 0=byte, 1=16b, 2=32b
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axi_awburst <= s_axi_awburst; // type, 0=fixed, 1=incr, 2=wrap
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end
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else if( s_axi_wvalid & s_axi_wready )
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if( axi_awburst == 2'b01 )
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begin //incremental burst
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// the write address for all the beats in the transaction are increments by the data width.
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// note: this should be based on awsize instead to support narrow bursts, i think.
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axi_awaddr[31:2] <= axi_awaddr[31:2] + 30'd1;
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//awaddr alignedto data width
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axi_awaddr[1:0] <= 2'b0;
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end // both fixed & wrapping types are treated as fixed, no update.
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end // else: !if(~s_axi_aresetn)
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//###################################################
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//#WRITE RESPONSE CHANNEL
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//###################################################
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always @ (posedge s_axi_aclk)
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if(~s_axi_aresetn)
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s_axi_wready <= 1'b0;
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else
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begin
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if( last_wr_beat )
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s_axi_wready <= 1'b0;
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else if( write_active )
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s_axi_wready <= ~txwr_wait;
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end
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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s_axi_bvalid <= 1'b0;
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s_axi_bresp[1:0] <= 2'b0;
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b_wait <= 1'b0;
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end
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else
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begin
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if( last_wr_beat )
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begin
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s_axi_bvalid <= 1'b1;
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s_axi_bresp[1:0] <= 2'b0; // 'okay' response
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b_wait <= ~s_axi_bready; // note: assumes bready will not drop without valid?
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end
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else if (s_axi_bready & s_axi_bvalid)
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begin
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s_axi_bvalid <= 1'b0;
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b_wait <= 1'b0;
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end
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end // else: !if( s_axi_aresetn == 1'b0 )
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//###################################################
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//#READ REQUEST CHANNEL
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//###################################################
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assign last_rd_beat = s_axi_rvalid & s_axi_rlast & s_axi_rready;
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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s_axi_arready <= 1'b0;
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read_active <= 1'b0;
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end
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else
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begin
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//arready
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if( ~s_axi_arready & ~read_active )
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s_axi_arready <= 1'b1;
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else if( s_axi_arvalid )
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s_axi_arready <= 1'b0;
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//read_active
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if( s_axi_arready & s_axi_arvalid )
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read_active <= 1'b1;
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else if( last_rd_beat )
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read_active <= 1'b0;
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end // else: !if( s_axi_aresetn == 1'b0 )
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//Read address channel state machine
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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axi_araddr[31:0] <= 0;
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axi_arlen <= 8'd0;
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axi_arburst <= 2'd0;
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axi_arsize[2:0] <= 3'b0;
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s_axi_rlast <= 1'b0;
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//s_axi_rid <= 'd0;
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end
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else
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begin
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if( s_axi_arready & s_axi_arvalid )
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begin
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axi_araddr[31:0] <= s_axi_araddr[31:0]; //NOTE: upper 2 bits get chopped by Zynq
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axi_arlen <= s_axi_arlen;
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axi_arburst <= s_axi_arburst;
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axi_arsize <= s_axi_arsize;
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s_axi_rlast <= ~(|s_axi_arlen);
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//s_axi_rid <= s_axi_arid;
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end
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else if( s_axi_rvalid & s_axi_rready)
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begin
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axi_arlen <= axi_arlen - 1;
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if(axi_arlen == 8'd1)
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s_axi_rlast <= 1'b1;
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if( s_axi_arburst == 2'b01)
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begin //incremental burst
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// the read address for all the beats in the transaction are increments by awsize
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// note: this should be based on awsize instead to support narrow bursts, i think?
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axi_araddr[31:2] <= axi_araddr[31:2] + 1;
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//araddr aligned to 4 byte boundary
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axi_araddr[1:0] <= 2'b0;
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//for awsize = 4 bytes (010)
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end
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end // if ( s_axi_rvalid & s_axi_rready)
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end // else: !if( s_axi_aresetn == 1'b0 )
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//###################################################
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//#WRITE REQUEST
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//###################################################
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assign txwr_write = 1'b1;
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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txwr_data_reg[31:0] <= 32'd0;
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txwr_dstaddr_reg[31:0] <= 32'd0;
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txwr_datamode_reg[1:0] <= 2'd0;
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txwr_access <= 1'b0;
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pre_wr_en <= 1'b0;
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end
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else
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begin
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pre_wr_en <= s_axi_wready & s_axi_wvalid;
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txwr_access <= pre_wr_en;
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txwr_datamode_reg[1:0] <= axi_awsize[1:0];
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txwr_dstaddr_reg[31:2] <= axi_awaddr[31:2]; //set lsbs of address based on write strobes
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if(s_axi_wstrb[0] | (axi_awsize[1:0]==2'b10))
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begin
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txwr_data_reg[31:0] <= s_axi_wdata[31:0];
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txwr_dstaddr_reg[1:0] <= 2'd0;
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end
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else if(s_axi_wstrb[1])
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begin
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txwr_data_reg[31:0] <= {8'd0, s_axi_wdata[31:8]};
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txwr_dstaddr_reg[1:0] <= 2'd1;
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end
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else if(s_axi_wstrb[2])
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begin
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txwr_data_reg[31:0] <= {16'd0, s_axi_wdata[31:16]};
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txwr_dstaddr_reg[1:0] <= 2'd2;
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end
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else
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begin
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txwr_data_reg[31:0] <= {24'd0, s_axi_wdata[31:24]};
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txwr_dstaddr_reg[1:0] <= 2'd3;
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end
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end // else: !if(~s_axi_aresetn)
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//Pipeline stage!
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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txwr_data[31:0] <= 32'd0;
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txwr_dstaddr[31:0] <= 32'd0;
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txwr_datamode[1:0] <= 2'd0;
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end
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else
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begin
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txwr_data[31:0] <= txwr_data_reg[31:0];
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txwr_dstaddr[31:0] <= txwr_dstaddr_reg[31:0];
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txwr_datamode[1:0] <= txwr_datamode_reg[1:0];
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end // else: !if(~s_axi_aresetn)
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//###################################################
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//#READ REQUEST (DATA CHANNEL)
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//###################################################
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// -- reads are performed by sending a read
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// -- request out the tx port and waiting for
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// -- data to come back through the rx read response port.
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// --
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// -- because elink reads are not generally
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// -- returned in order, we will only allow
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// -- one at a time.
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assign txrd_write = 1'b0;
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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txrd_access <= 1'b0;
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txrd_datamode[1:0] <= 2'd0;
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txrd_dstaddr[31:0] <= 32'd0;
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txrd_srcaddr[31:0] <= 32'd0;
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ractive_reg <= 1'b0;
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rnext <= 1'b0;
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end
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else
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begin
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ractive_reg <= read_active;
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rnext <= s_axi_rvalid & s_axi_rready & ~s_axi_rlast;
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txrd_access <= ( ~ractive_reg & read_active ) | rnext;
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txrd_datamode[1:0] <= axi_arsize[1:0];
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txrd_dstaddr[31:0] <= axi_araddr[31:0];
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txrd_srcaddr[31:0] <= {RETURN_ADDR, 16'd0};
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//TODO: use arid+srcaddr for out of order ?
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end
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//###################################################
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//#READ RESPONSE (DATA CHANNEL)
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//###################################################
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//Read response AXI state machine
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//Only one outstanding read
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assign rxrr_wait = 1'b0;
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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s_axi_rvalid <= 1'b0;
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s_axi_rdata[31:0] <= 32'd0;
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s_axi_rresp <= 2'd0;
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end
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else
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begin
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if( rxrr_access )
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begin
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s_axi_rvalid <= 1'b1;
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s_axi_rresp <= 2'd0;
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|
case( axi_arsize[1:0] )
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2'b00: s_axi_rdata[31:0] <= {4{rxrr_data[7:0]}}; //8-bit
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2'b01: s_axi_rdata[31:0] <= {2{rxrr_data[15:0]}}; //16-bit
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default: s_axi_rdata[31:0] <= rxrr_data[31:0]; //32-bit
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endcase // case ( axi_arsize[1:0] )
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|
end
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|
else if( s_axi_rready )
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s_axi_rvalid <= 1'b0;
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end // else: !if( s_axi_aresetn == 1'b0 )
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|
|
|
endmodule // esaxi
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|
|
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/*
|
|
Copyright (C) 2014 Adapteva, Inc.
|
|
|
|
Contributed by Andreas Olofsson <andreas@adapteva.com>
|
|
Contributed by Fred Huettig <fred@adapteva.com>
|
|
|
|
This program is free software: you can redistribute it and/or modify
|
|
it under the terms of the GNU General Public License as published by
|
|
the Free Software Foundation, either version 3 of the License, or
|
|
(at your option) any later version.This program is distributed in the hope
|
|
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
|
|
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
GNU General Public License for more details. You should have received a copy
|
|
of the GNU General Public License along with this program (see the file
|
|
COPYING). If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|