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b8c699fb22
-Communication with IO is with "packet format" -No need to invent a 64 bit format just for stupid OSERDES
149 lines
4.0 KiB
Verilog
149 lines
4.0 KiB
Verilog
module etx_protocol (/*AUTOARG*/
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// Outputs
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etx_rd_wait, etx_wr_wait, tx_packet, tx_access, tx_burst,
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// Inputs
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reset, clk, etx_access, etx_packet, tx_enable, gpio_data,
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gpio_enable, tx_io_wait, tx_rd_wait, tx_wr_wait
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);
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parameter PW = 104;
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parameter AW = 32;
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parameter DW = 32;
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parameter ID = 12'h000;
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//Clock/reset
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input reset;
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input clk;
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//System side
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input etx_access;
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input [PW-1:0] etx_packet;
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//Pushback signals
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output etx_rd_wait;
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output etx_wr_wait;
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//Enble transmit
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input tx_enable; //transmit enable
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input [8:0] gpio_data; //TODO
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input gpio_enable; //TODO
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//Interface to IO
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output [PW-1:0] tx_packet;
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output tx_access;
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output tx_burst;
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input tx_io_wait;
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input tx_rd_wait; // The wait signals are passed through
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input tx_wr_wait; // to the emesh interfaces
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//###################################################################
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//# Local regs & wires
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//###################################################################
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reg tx_access;
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reg [PW-1:0] tx_packet;
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reg tx_burst;
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wire tx_rd_wait_sync;
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wire tx_wr_wait_sync;
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wire etx_write;
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wire [1:0] etx_datamode;
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wire [3:0] etx_ctrlmode;
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wire [AW-1:0] etx_dstaddr;
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wire [DW-1:0] etx_data;
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wire [AW-1:0] etx_srcaddr;
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wire etx_valid;
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reg etx_io_wait;
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//packet to emesh bundle
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packet2emesh p2m (
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// Outputs
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.access_out (),
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.write_out (etx_write),
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.datamode_out (etx_datamode[1:0]),
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.ctrlmode_out (etx_ctrlmode[3:0]),
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.dstaddr_out (etx_dstaddr[31:0]),
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.data_out (etx_data[31:0]),
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.srcaddr_out (etx_srcaddr[31:0]),
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// Inputs
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.packet_in (etx_packet[PW-1:0])
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);
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//Only set valid if not wait
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assign etx_valid = (tx_enable & etx_access & ~(etx_dstaddr[31:20]==ID)) &
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((etx_write & ~tx_wr_wait_sync) |
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(~etx_write & ~tx_rd_wait_sync)
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);
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//Prepare transaction / with burst
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always @ (posedge clk or posedge reset)
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if(reset)
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begin
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tx_packet[PW-1:0] <= 'b0;
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tx_access <= 1'b0;
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tx_burst <= 1'b0;//TODO
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end
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else if(~tx_io_wait)
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begin
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tx_packet[PW-1:0] <= etx_packet[PW-1:0];
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tx_access <= etx_valid;
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tx_burst <= 1'b0;//TODO
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end
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//#############################
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//# Wait signals (async)
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//#############################
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synchronizer #(.DW(1)) rd_sync (// Outputs
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.out (tx_rd_wait_sync),
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// Inputs
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.in (tx_rd_wait),
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.clk (clk),
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.reset (reset)
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);
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synchronizer #(.DW(1)) wr_sync (// Outputs
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.out (tx_wr_wait_sync),
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// Inputs
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.in (tx_wr_wait),
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.clk (clk),
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.reset (reset)
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);
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//Stall for all etx pipeline
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assign etx_wr_wait = tx_wr_wait_sync | tx_io_wait;
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assign etx_rd_wait = tx_rd_wait_sync | tx_io_wait;
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endmodule // etx_protocol
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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/*
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File: etx_protocol.v
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This file is part of the Parallella Project.
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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