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45 lines
885 B
Verilog
45 lines
885 B
Verilog
//Variable pipeline depth syncrhonizer
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module dsync (/*AUTOARG*/
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// Outputs
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dout,
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// Inputs
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clk, din
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);
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parameter PS = 2; //number of sync pipeline stages
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parameter DW = 1; //number of bits to synchronize
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input clk;
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input [DW-1:0] din;
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output [DW-1:0] dout;
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`ifdef TARGET_SIM
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reg [DW-1:0] sync_pipe[PS-1:0];
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`else
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(* ASYNC_REG = "TRUE" *) (* DONT_TOUCH = "TRUE" *) reg [DW-1:0] sync_pipe[PS-1:0];
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`endif
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genvar i;
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generate
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for(i=0;i<PS;i=i+1)
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if(i==0)
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begin
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always @ (posedge clk)
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sync_pipe[0][DW-1:0] <= din[DW-1:0];
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end
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else
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begin
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always @ (posedge clk )
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sync_pipe[i][DW-1:0] <= sync_pipe[i-1][DW-1:0];
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end // else: !if(i==0)
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endgenerate
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assign dout[DW-1:0] = sync_pipe[PS-1][DW-1:0];
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endmodule // dsync
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