FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity
oh/asiclib
History
aolofsson 79b1eb5b6c Adding README for asiclib
2021-08-02 18:00:13 -04:00
..
hdl
Fixing typo bug in csa32
2021-07-28 18:27:21 -04:00
scripts
Adding asiclib scripts directory
2021-07-28 08:48:15 -04:00
README.md
Adding README for asiclib
2021-08-02 18:00:13 -04:00

README.md

ASICLIB

  • ASICLIB is a library of low level "standard" cells hard-coded to a specific PDK.
  • The library is meant to be linked in at compile time based on the foundry being targeted.
  • The cells do not have any dependancies.