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19fa611bb9
- adding more chip code - pushing memory stuff into common - making common "oh_" naming class -
29 lines
497 B
Verilog
29 lines
497 B
Verilog
//CSA4:2 Compressor
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module oh_csa42 (/*AUTOARG*/
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// Outputs
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s, c, c_out,
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// Inputs
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in0, in1, in2, in3, c_in
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);
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input in0;
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input in1;
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input in2;
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input in3;
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input c_in;
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output s;
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output c;
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output c_out;
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wire s_int;
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assign s = in0 ^ in1 ^in2 ^in3 ^ c_in;
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assign s_int = in1 ^ in2 ^ in3;
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assign c = (in0 & s_int) | (in0 & c_in) | (s_int & c_in);
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assign c_out = (in1 & in2) | (in1 & in3) | (in2 & in3);
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endmodule // oh_csa42
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