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19fa611bb9
- adding more chip code - pushing memory stuff into common - making common "oh_" naming class -
36 lines
723 B
Verilog
36 lines
723 B
Verilog
//CSA6:2 Compressor
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module oh_csa62 (/*AUTOARG*/
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// Outputs
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s, c, c_out0, c_out1, c_out2,
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// Inputs
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in0, in1, in2, in3, in4, in5, c_in0, c_in1, c_in2
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);
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input in0;
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input in1;
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input in2;
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input in3;
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input in4;
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input in5;
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input c_in0;
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input c_in1;
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input c_in2;
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output s;
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output c;
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output c_out0;
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output c_out1;
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output c_out2;
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wire s_int0;
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wire s_int1;
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oh_csa32 csa32_0 (.in0(in0),.in1(in1),.in2(in2),.c(c_out0),.s(s_int0));
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oh_csa32 csa32_1 (.in0(in3),.in1(in4),.in2(in5),.c(c_out1),.s(s_int1));
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oh_csa42 csa42 (.in0(s_int0),.in1(s_int1),.in2(c_in0),.in3(c_in1),.c_in(c_in2),
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.c_out(c_out2),.c(c),.s(s));
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endmodule // oh_csa62
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