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87 lines
2.0 KiB
Verilog
87 lines
2.0 KiB
Verilog
/*
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########################################################################
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Generic small FIFO using distributed memory
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Caution: There is no protection against overflow or underflow,
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driving logic should avoid wen on full or ren on empty.
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########################################################################
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*/
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module fifo_sync
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#(
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// Address width (must be 5 => 32-deep FIFO)??
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parameter AW = 5,
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// Data width
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parameter DW = 16
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)
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(
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input clk,
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input reset,
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input [DW-1:0] wr_data,
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input wr_en,
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input rd_en,
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output wire [DW-1:0] rd_data,
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output reg rd_empty,
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output reg wr_full
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);
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reg [AW-1:0] wr_addr;
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reg [AW-1:0] rd_addr;
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reg [AW-1:0] count;
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always @ ( posedge clk ) begin
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if( reset )
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begin
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wr_addr[AW-1:0] <= 'd0;
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rd_addr[AW-1:0] <= 'b0;
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count[AW-1:0] <= 'b0;
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rd_empty <= 1'b1;
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wr_full <= 1'b0;
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end else
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begin
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if( wr_en & rd_en )
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begin
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wr_addr <= wr_addr + 'd1;
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rd_addr <= rd_addr + 'd1;
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end
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else if( wr_en )
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begin
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wr_addr <= wr_addr + 'd1;
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count <= count + 'd1;
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rd_empty <= 1'b0;
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if( & count )
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wr_full <= 1'b1;
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end
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else if( rd_en )
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begin
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rd_addr <= rd_addr + 'd1;
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count <= count - 'd1;
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wr_full <= 1'b0;
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if( count == 'd1 )
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rd_empty <= 1'b1;
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end
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end
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end
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// GENERIC DUAL PORTED MEMORY
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defparam mem.DW=DW;
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defparam mem.AW=AW;
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memory_dp mem (
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// Outputs
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.rd_data (rd_data[DW-1:0]),
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// Inputs
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.wr_clk (clk),
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.wr_en ({(DW/8){wr_en}}),
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.wr_addr (wr_addr[AW-1:0]),
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.wr_data (wr_data[DW-1:0]),
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.rd_clk (clk),
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.rd_en (rd_en),
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.rd_addr (rd_addr[AW-1:0]));
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endmodule // fifo_sync
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// Local Variables:
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// verilog-library-directories:(".")
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// End:
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