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19fa611bb9
- adding more chip code - pushing memory stuff into common - making common "oh_" naming class -
54 lines
1.2 KiB
Verilog
54 lines
1.2 KiB
Verilog
// FUNCTION: Transfers a pulse on clkin domain to a pulse on clkout domain
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// !!!WARNING: "din" pulse width must be greater than clkout width!!!
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module oh_pulse2pulse(/*AUTOARG*/
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// Outputs
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dout,
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// Inputs
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nrstin, din, clkin, nrstout, clkout
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);
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//input clock domain
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input nrstin; //input domain reset
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input din; //input pulse (one clock cycle)
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input clkin; //input clock
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//output clock domain
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input nrstout; //output domain reset
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input clkout; //output clock
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output dout; //output pulse (one clock cycle)
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reg toggle_reg;
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reg pulse_reg;
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wire toggle;
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//pulse to toggle
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assign toggle = din ? ~toggle_reg : toggle_reg;
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always @ (posedge clkin)
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if(~nrstin)
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toggle_reg <= 1'b0;
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else
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toggle_reg <= toggle;
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//metastability synchronizer
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oh_dsync #(1) sync(.dout (toggle_sync),
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.din (toggle),
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.clk (clkout)
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);
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//toogle to pulse
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always @ (posedge clkout)
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if(!nrstout)
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pulse_reg <= 1'b0;
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else
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pulse_reg <= toggle_sync;
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assign dout = pulse_reg ^ toggle_sync;
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endmodule // oh_pulse2pulse
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