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99 lines
3.2 KiB
Verilog
99 lines
3.2 KiB
Verilog
/*WARNING: INCOMPLETE MODEL, DON'T USE. I RECOMMEND AGAINST USING THIS
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*BLOCK ALL TOGETHER. NOT OPEN SOURCE FRIENDLY /AO
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*/
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module OSERDESE2 ( /*AUTOARG*/
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// Outputs
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OFB, OQ, SHIFTOUT1, SHIFTOUT2, TBYTEOUT, TFB, TQ,
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// Inputs
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CLK, CLKDIV, D1, D2, D3, D4, D5, D6, D7, D8, OCE, RST, SHIFTIN1,
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SHIFTIN2, T1, T2, T3, T4, TBYTEIN, TCE
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);
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parameter DATA_RATE_OQ=0;
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parameter DATA_RATE_TQ=0;
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parameter DATA_WIDTH=0;
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parameter INIT_OQ=0;
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parameter INIT_TQ=0;
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parameter SERDES_MODE=0;
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parameter SRVAL_OQ=0;
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parameter SRVAL_TQ=0;
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parameter TBYTE_CTL=0;
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parameter TBYTE_SRC=0;
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parameter TRISTATE_WIDTH=0;
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output OFB; // output feedback port
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output OQ; // data output port, D1 appears first
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output SHIFTOUT1; // connect to shift in of master
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output SHIFTOUT2; // connect to shift in of master
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output TBYTEOUT; // byte group tristate output to IOB
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output TFB; // 3-state control output for ODELAYE2
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output TQ; // 3-state control output
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input CLK; // high speed shift out clock
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input CLKDIV; // low speed clock (/4 for example)
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input D1; // first bit to shift out
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input D2; //
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input D3; //
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input D4; //
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input D5; //
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input D6; //
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input D7; //
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input D8; //
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input OCE; // active high clock enable for datapath
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input RST; // async reset, all output flops driven low
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input SHIFTIN1; // connect to shift out of other
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input SHIFTIN2; // connect to shift out of other
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input T1; // parallel 3-state signals
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input T2; // ??why 4??
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input T3; //
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input T4; //
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input TBYTEIN; // byte group tristate input
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input TCE; // active high clock enable for 3-state
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//Statemachine
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reg [2:0] state;
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reg [7:0] buffer;
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reg [1:0] clkdiv_sample;
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reg [3:0] even;
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reg [3:0] odd;
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//parallel sample
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always @ (posedge CLKDIV)
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buffer[7:0]<={D8,D7,D6,D5,D4,D3,D2,D1};
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//sample clkdiv
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always @ (negedge CLK)
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clkdiv_sample[1:0] <= {clkdiv_sample[0],CLKDIV};
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//shift on second consective clk rising edge that clkdi_sample==0
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wire load_parallel = (clkdiv_sample[1:0]==2'b00);
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always @ (posedge CLK)
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if(load_parallel)
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even[3:0]<={buffer[6],buffer[4],buffer[2],buffer[0]};
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else
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even[3:0]<={1'b0,even[3:1]};
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always @ (posedge CLK)
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if(load_parallel)
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odd[3:0]<={buffer[7],buffer[5],buffer[3],buffer[1]};
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else
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odd[3:0]<={1'b0,odd[3:1]};
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assign OQ = CLK ? even[0] : odd[0];
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//setting other outputs
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assign OFB = 1'b0;
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assign TQ = 1'b0;
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assign TBYTEOUT = 1'b0;
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assign SHIFTOUT1 = 1'b0;
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assign SHIFTOUT2 = 1'b0;
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assign TFB = 1'b0;
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endmodule // OSERDESE2
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