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oh/asiclib/hdl/asic_csa42.v
aolofsson 289024fd89 Flattening directory tree (again)
- Creating an arbitrary 'src' directory really doesn't help much...
- Goal is to make each folder self contained
- Make meta repos and individual repos have the same directory structure
2022-06-21 14:48:48 -04:00

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Verilog

//#############################################################################
//# Function: Carry Save Adder (4:2) (aka 5:3) #
//# Copyright: OH Project Authors. ALl rights Reserved. #
//# License: MIT (see LICENSE file in OH repository) #
//#############################################################################
module asic_csa42 #(parameter PROP = "DEFAULT") ( input a,
input b,
input c,
input d,
input cin,
output sum,
output carry,
output cout
);
assign cout = (a & b) | (b & c) | (a & c);
assign sumint = a ^ b ^ c;
assign sum = cin ^ d ^ sumint;
assign carry = (cin & d) | (cin & sumint) | (d & sumint);
endmodule