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- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
95 lines
2.8 KiB
Verilog
95 lines
2.8 KiB
Verilog
module axislave_stub (/*AUTOARG*/
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// Outputs
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s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
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s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp, s_axi_rvalid,
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s_axi_wready,
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// Inputs
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s_axi_aclk, s_axi_aresetn, s_axi_arid, s_axi_araddr, s_axi_arburst,
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s_axi_arcache, s_axi_arlock, s_axi_arlen, s_axi_arprot,
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s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid, s_axi_awaddr,
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s_axi_awburst, s_axi_awcache, s_axi_awlock, s_axi_awlen,
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s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
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s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast,
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s_axi_wstrb, s_axi_wvalid
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);
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parameter S_IDW = 12;
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/*****************************/
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/*AXI slave interface */
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/*****************************/
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//Clock and reset
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input s_axi_aclk;
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input s_axi_aresetn;
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//Read address channel
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input [S_IDW-1:0] s_axi_arid; //write address ID
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input [31:0] s_axi_araddr;
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input [1:0] s_axi_arburst;
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input [3:0] s_axi_arcache;
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input s_axi_arlock;
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input [7:0] s_axi_arlen;
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input [2:0] s_axi_arprot;
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input [3:0] s_axi_arqos;
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output s_axi_arready;
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input [2:0] s_axi_arsize;
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input s_axi_arvalid;
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//Write address channel
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input [S_IDW-1:0] s_axi_awid; //write address ID
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input [31:0] s_axi_awaddr;
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input [1:0] s_axi_awburst;
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input [3:0] s_axi_awcache;
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input s_axi_awlock;
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input [7:0] s_axi_awlen;
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input [2:0] s_axi_awprot;
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input [3:0] s_axi_awqos;
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input [2:0] s_axi_awsize;
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input s_axi_awvalid;
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output s_axi_awready;
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//Buffered write response channel
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output [S_IDW-1:0] s_axi_bid; //write address ID
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output [1:0] s_axi_bresp;
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output s_axi_bvalid;
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input s_axi_bready;
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//Read channel
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output [S_IDW-1:0] s_axi_rid; //write address ID
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output [31:0] s_axi_rdata;
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output s_axi_rlast;
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output [1:0] s_axi_rresp;
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output s_axi_rvalid;
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input s_axi_rready;
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//Write channel
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input [S_IDW-1:0] s_axi_wid; //write address ID
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input [31:0] s_axi_wdata;
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input s_axi_wlast;
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input [3:0] s_axi_wstrb;
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input s_axi_wvalid;
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output s_axi_wready;
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//read address chanel
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assign s_axi_arready = 'b0;
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//write address channel
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assign s_axi_awready = 'b0;
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//buffered write response
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assign s_axi_bid[S_IDW-1:0] = 'b0;
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assign s_axi_bresp[1:0] = 'b0;
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//read channel
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assign s_axi_rid[S_IDW-1:0] = 'b0;
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assign s_axi_rdata[31:0] = 'b0;
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assign s_axi_rlast = 'b0;
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assign s_axi_rresp[1:0] = 'b0;
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assign s_axi_rvalid = 'b0;
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//write channel
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assign s_axi_wready = 'b0;
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endmodule // saxi_tieoff
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