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143 lines
5.1 KiB
Verilog
143 lines
5.1 KiB
Verilog
//#############################################################################
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//# Purpose: SPI top (configurable as master or slave) #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module spi #( parameter AW = 32, // address width
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parameter PW = 104, // packet size
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parameter UREGS = 13 // number of user slave regs
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)
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(//clk, reset, irq
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input nreset, // asynch active low reset
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input clk, // core clock
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input hw_en, // block enable pin
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output spi_irq, // interrupt output
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//packet from core
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input access_in, // access from core
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input [PW-1:0] packet_in, // packet from core
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input wait_in, // pushback from io
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//packet to core
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output access_out, // access to core
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output [PW-1:0] packet_out, // packet to core
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output wait_out, // pushback from core
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//master io interface
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output m_sclk, // master clock
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output m_mosi, // master output
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output m_ss, // slave select
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input m_miso, // master input
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//slave io interface
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input s_sclk, // slave clock
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input s_mosi, // slave input
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input s_ss, // slave select
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output s_miso // slave output
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);
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//###############
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//# LOCAL WIRES
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//###############
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire m_access_out; // From spi_master of spi_master.v
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wire [PW-1:0] m_packet_out; // From spi_master of spi_master.v
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wire m_wait_out; // From spi_master of spi_master.v
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wire s_access_out; // From spi_slave of spi_slave.v
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wire [PW-1:0] s_packet_out; // From spi_slave of spi_slave.v
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wire [511:0] s_spi_regs; // From spi_slave of spi_slave.v
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wire s_wait_out; // From spi_slave of spi_slave.v
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// End of automatics
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//###########################################################
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//# SPI SLACE
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//###########################################################
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/*spi_master AUTO_TEMPLATE (.clk (clk),
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.nreset (nreset),
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.hw_en (hw_en),
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.\(.*\)_in (\1_in[]),
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.\(.*\) (m_\1[]),
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);
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*/
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spi_master #(.AW(AW),
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.PW(PW))
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spi_master (/*AUTOINST*/
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// Outputs
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.sclk (m_sclk), // Templated
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.mosi (m_mosi), // Templated
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.ss (m_ss), // Templated
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.wait_out (m_wait_out), // Templated
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.access_out (m_access_out), // Templated
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.packet_out (m_packet_out[PW-1:0]), // Templated
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// Inputs
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.clk (clk), // Templated
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.nreset (nreset), // Templated
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.hw_en (hw_en), // Templated
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.miso (m_miso), // Templated
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.access_in (access_in), // Templated
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.packet_in (packet_in[PW-1:0]), // Templated
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.wait_in (wait_in)); // Templated
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//###########################################################
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//# SPI SLAVE
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//###########################################################
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/*spi_slave AUTO_TEMPLATE (.clk (clk),
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.spi_irq (spi_irq),
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.nreset (nreset),
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.hw_en (hw_en),
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.\(.*\)_in (\1_in[]),
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.\(.*\) (s_\1[]),
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);
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*/
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spi_slave #(.AW(AW),
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.PW(PW),
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.UREGS(UREGS))
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spi_slave (/*AUTOINST*/
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// Outputs
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.spi_regs (s_spi_regs[511:0]), // Templated
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.spi_irq (spi_irq), // Templated
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.miso (s_miso), // Templated
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.access_out (s_access_out), // Templated
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.packet_out (s_packet_out[PW-1:0]), // Templated
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.wait_out (s_wait_out), // Templated
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// Inputs
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.clk (clk), // Templated
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.nreset (nreset), // Templated
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.hw_en (hw_en), // Templated
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.sclk (s_sclk), // Templated
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.mosi (s_mosi), // Templated
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.ss (s_ss), // Templated
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.wait_in (wait_in), // Templated
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.access_in (access_in), // Templated
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.packet_in (packet_in[PW-1:0])); // Templated
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//###########################################################
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//# EMESH MUX
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//###########################################################
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assign wait_out = s_wait_out | m_wait_out;
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emesh_mux #(.N(2),
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.AW(AW),
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.PW(PW))
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emesh_mux (// Outputs
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.wait_out (),
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.access_out (access_out),
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.access_in ({s_access_out,m_access_out}),
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.packet_in ({s_packet_out[PW-1:0],m_packet_out[PW-1:0]}),
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.wait_in (wait_in)
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);
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endmodule // spi
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../emesh/hdl")
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// End:
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