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264 lines
8.8 KiB
Verilog
264 lines
8.8 KiB
Verilog
`include "pic_regmap.v"
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//###########################################################################
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//# IRQC: Simple nessted interrupt controller
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//#
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//############################################################################
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module pic(/*AUTOARG*/
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// Outputs
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ic_flush, ic_iret_reg, ic_imask_reg, ic_ilat_reg, ic_ipend_reg,
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ic_irq, ic_irq_addr,
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// Inputs
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clk, nreset, reg_write, reg_addr, reg_wdata, ext_irq,
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sq_pc_next_ra, de_rti_e1, sq_global_irq_en, sq_ic_wait
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);
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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//Parameters
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parameter LAW = 32;
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parameter IRQW = 10;
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//Basic Interface
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input clk; //main clock
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input nreset; //active low async reset
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//Sysreg Write Access
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input reg_write; //write signal
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input [5:0] reg_addr; //addr[5:0]
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input [31:0] reg_wdata; //data input
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//Control signals
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input [IRQW-1:0] ext_irq; //interrupt signals
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input [LAW-1:0] sq_pc_next_ra; //PC to save to IRET
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input de_rti_e1; //jump to IRET
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input sq_global_irq_en; //disables all interrupts
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input sq_ic_wait; //wait until it's safe to interrupt (delete?)
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output ic_flush; //flush pipeline to get rid if all instructions
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//Register Read Outputs
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output [LAW-1:0] ic_iret_reg; //interrupt return register
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output [IRQW-1:0] ic_imask_reg; //interrupt mask register
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output [IRQW-1:0] ic_ilat_reg; //latched ext_irq signals (but not started)
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output [IRQW-1:0] ic_ipend_reg; //interrrupts pending/active
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//Interrupt Vector
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output ic_irq; //tells core to jump to adress in irq_addr
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output [LAW-1:0] ic_irq_addr; //interrupt vector
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//#####################################################################
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//# BODY
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//#####################################################################
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//For loop integers
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integer i,j,m1,m2,n1,n2,p;
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//Control registers
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reg [LAW-1:0] ic_iret_reg;
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reg [IRQW-1:0] ic_ilat_reg;
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reg [IRQW-1:0] ic_imask_reg;
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reg [IRQW-1:0] ic_ipend_reg;
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reg [LAW-1:0] ic_irq_addr;
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//Functions
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reg [IRQW-1:0] ic_ilat_in;
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reg [IRQW-1:0] ic_ilat_priority_en_n;
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reg [IRQW-1:0] ic_ipend_priority_en_n;
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reg [IRQW-1:0] ic_irq_shadow;
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reg [IRQW-1:0] ic_irq_entry;
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//Wires
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wire [IRQW-1:0] ic_masked_ilat;
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wire [LAW-1:0] ic_ivt[IRQW-1:0];
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wire [IRQW-1:0] ic_ipend_in;//changed to generate
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wire [IRQW:0] ic_ipend_shifted_reg;
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wire [IRQW-1:0] ic_imask_in;
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wire [IRQW-1:0] ic_irq_select;
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wire [IRQW-1:0] ic_global_en;
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wire [IRQW-1:0] ic_event;
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wire [IRQW-1:0] ic_ilat_set_data;
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wire [IRQW-1:0] ic_ilat_clear_data;
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wire ic_write_imask;
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wire ic_write_ipend;
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wire ic_write_ilat;
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wire ic_write_ilatset;
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wire ic_write_ilatclr;
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wire ic_write_iret;
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//###########################
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//ACCESS DECODE
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//###########################
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assign ic_write_imask = reg_write &(reg_addr[5:0] ==`ECORE_IMASK);
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assign ic_write_ipend = reg_write &(reg_addr[5:0] ==`ECORE_IPEND);
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assign ic_write_ilat = reg_write &(reg_addr[5:0] ==`ECORE_ILAT);
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assign ic_write_ilatset = reg_write &(reg_addr[5:0] ==`ECORE_ILATST);
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assign ic_write_ilatclr = reg_write &(reg_addr[5:0] ==`ECORE_ILATCL);
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assign ic_write_iret = reg_write & reg_addr[5:0] ==`ECORE_IRET;
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//###########################
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//# RISING EDGE DETECTOR
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//###########################
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always @ (posedge clk)
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ic_irq_shadow[IRQW-1:0]= ext_irq[IRQW-1:0] ;
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assign ic_event[IRQW-1:0] = ext_irq[IRQW-1:0] & ~ic_irq_shadow[IRQW-1:0] ;
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//###########################
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//# ILAT
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//###########################
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assign ic_ilat_set_data[IRQW-1:0] = reg_wdata[IRQW-1:0] |
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ic_ilat_reg[IRQW-1:0];
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assign ic_ilat_clear_data[IRQW-1:0] = ~reg_wdata[IRQW-1:0] &
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ic_ilat_reg[IRQW-1:0];
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always @*
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for(i=0;i<IRQW;i=i+1)
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ic_ilat_in[i] =(ic_write_ilat & reg_wdata[i])| // explicit write
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(ic_write_ilatset & ic_ilat_set_data[i]) | // ilatset
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(ic_event[i]) | // irq signal
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(ic_ilat_reg[i] &
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~(ic_write_ilatclr & reg_wdata[i]) &
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(sq_ic_wait | ~ic_irq_entry[i])
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); //isr entry clear
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//Don't clock gate the ILAT, should always be ready to recieve
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always @ (posedge clk or negedge nreset)
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if (!nreset)
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ic_ilat_reg[IRQW-1:0] <= 'b0;
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else
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ic_ilat_reg[IRQW-1:0] <= ic_ilat_in[IRQW-1:0];
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//###########################
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//# IPEND
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//###########################
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assign ic_ipend_shifted_reg[IRQW:0] = {ic_ipend_reg[IRQW-1:0],1'b0};
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genvar q;
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generate
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for(q=IRQW-1;q>=0;q=q-1) begin : gen_ipend
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assign ic_ipend_in[q]=(ic_irq_entry[q]) |
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(ic_ipend_reg[q] & ~de_rti_e1) |
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(|ic_ipend_shifted_reg[q:0]); //BUG?????
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end
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endgenerate
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always @ (posedge clk or negedge nreset)
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if (!nreset)
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ic_ipend_reg[IRQW-1:0] <= 'b0;
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else if(ic_write_ipend)
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ic_ipend_reg[IRQW-1:0] <= reg_wdata[IRQW-1:0];
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else
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ic_ipend_reg[IRQW-1:0] <= ic_ipend_in[IRQW-1:0];
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//###########################
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//# IMASK
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//###########################
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assign ic_imask_in[IRQW-1:0] = ic_write_imask ? reg_wdata[IRQW-1:0] :
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ic_imask_reg[IRQW-1:0];
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always @ (posedge clk or negedge nreset)
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if (!nreset)
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ic_imask_reg[IRQW-1:0] <= 'b0;
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else if(ic_write_imask)
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ic_imask_reg[IRQW-1:0] <= reg_wdata[IRQW-1:0];
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//###########################
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//# IRET
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//###########################
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always @ (posedge clk)
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if(ic_flush)
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ic_iret_reg[LAW-1:0] <= sq_pc_next_ra[LAW-1:0];
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else if(ic_write_iret)
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ic_iret_reg[LAW-1:0] <= reg_wdata[LAW-1:0];
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//###########################
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//# IRQ VECTOR TABLE
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//###########################
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genvar k;
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generate
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for(k=0;k<IRQW;k=k+1) begin: irqs
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assign ic_ivt[k]=(`IRQ_VECTOR_TABLE+4*k);
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end
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endgenerate
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//mux
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always @*
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begin
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ic_irq_addr[LAW-1:0] = {(LAW){1'b0}};
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for(p=0;p<IRQW;p=p+1)
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ic_irq_addr[LAW-1:0] = ic_irq_addr[LAW-1:0] |
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({(LAW){ic_irq_entry[p]}} & ic_ivt[p]);
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end
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//###########################
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//# PRIORITY CONTROLLER
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//###########################
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//Masking interrupts
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assign ic_masked_ilat[IRQW-1:0] = ic_ilat_reg[IRQW-1:0] &
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~ic_imask_reg[IRQW-1:0];
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//Interrupt sent to sequencer if:
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//1.) no bit set in ipend for anything at that bit level or below
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//2.) global interrupt enable set
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//3.) no valid interrupt set at any bit lower than this one
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//ILAT PRIORITY
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//Keeps track of all higher priority ILATs that are not masked
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//This circuit is needed for the case when interrupts arrive simulataneously
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always @*
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begin
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for(m1=IRQW-1;m1>0;m1=m1-1)
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begin
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ic_ilat_priority_en_n[m1]=1'b0;
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for(m2=m1-1;m2>=0;m2=m2-1)
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ic_ilat_priority_en_n[m1]=ic_ilat_priority_en_n[m1] | ic_masked_ilat[m2];
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end
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//No priority needed for bit[0], highest priority, so it's always enabled
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ic_ilat_priority_en_n[0]=1'b0;
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end
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//IPEND PRIORITY
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always @*
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begin
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for(n1=IRQW-1;n1>=0;n1=n1-1)
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begin
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ic_ipend_priority_en_n[n1]=1'b0;
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for(n2=n1;n2>=0;n2=n2-1)
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ic_ipend_priority_en_n[n1]=ic_ipend_priority_en_n[n1] | ic_ipend_reg[n2];//ic_ipend_reg[n2-1]
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end
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//Bit zero has no IPEND priority: NO
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//ic_ipend_priority_en_n[0]=1'b0;
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end
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//Outgoing Interrupt (to sequencer)
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assign ic_irq_select[IRQW-1:0]= ic_masked_ilat[IRQW-1:0] & //only if the ILAT bit is not masked by IMASK
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~ic_ilat_priority_en_n[IRQW-1:0] & //only if there is no masked ilat bit <current
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~ic_ipend_priority_en_n[IRQW-1:0] & //only if there is no ipend bit <=current
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{(IRQW){sq_global_irq_en}}; //global vector for nested interrupts
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//Pipelining interrupt to account for stall signal
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//TODO: Understand this better...
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always @ (posedge clk)
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if(~sq_ic_wait)//includes fetch wait
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ic_irq_entry[IRQW-1:0] <= ic_irq_select[IRQW-1:0];// & ~ic_irq_entry[IRQW-1:0] ;
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assign ic_irq =|(ic_irq_entry[IRQW-1:0]);
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//Flush for one cycle interrupt pulse
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assign ic_flush =|(ic_irq_select[IRQW-1:0]);
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endmodule // interrupt_controller
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