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289024fd89
- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
137 lines
4.0 KiB
Verilog
137 lines
4.0 KiB
Verilog
//#############################################################################
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//# Purpose: SPI Master Transmit Fifo #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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`include "spi_regmap.vh"
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module spi_master_fifo #(parameter DEPTH = 16, // fifo entries
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parameter AW = 32, // address width
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parameter PW = 104, // input packet width
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parameter SW = 8 // io packet width
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)
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(
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//clk,reset, cfg
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input clk, // clk
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input nreset, // async active low reset
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input spi_en, // spi enable
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output fifo_prog_full, // fifo full indicator for status
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// Incoming interface
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input access_in, // access by core
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input [PW-1:0] packet_in, // packet from core
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output wait_out, // pushback to core
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// IO interface
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input fifo_read, // pull a byte to IO
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output fifo_empty, // fifo is empty
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output [SW-1:0] fifo_dout // byte for IO
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);
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localparam FAW = $clog2(DEPTH); // fifo address width
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localparam SRW = $clog2(PW/SW); // serialization factor
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//###############
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//# LOCAL WIRES
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//###############
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wire [7:0] datasize;
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wire [PW-1:0] tx_data;
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wire [SW-1:0] fifo_din;
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wire tx_write;
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wire fifo_wait;
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wire fifo_wr;
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wire fifo_full;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] data_in; // From p2e of packet2emesh.v
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wire [1:0] datamode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
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wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
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wire write_in; // From p2e of packet2emesh.v
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// End of automatics
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//##################################
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//# DECODE
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//###################################
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packet2emesh #(.AW(AW),
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.PW(PW))
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p2e (/*AUTOINST*/
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// Outputs
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.write_in (write_in),
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.datamode_in (datamode_in[1:0]),
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.ctrlmode_in (ctrlmode_in[4:0]),
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.dstaddr_in (dstaddr_in[AW-1:0]),
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.srcaddr_in (srcaddr_in[AW-1:0]),
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.data_in (data_in[AW-1:0]),
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// Inputs
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.packet_in (packet_in[PW-1:0]));
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assign datasize[7:0] = (1<<datamode_in[1:0]);
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assign tx_write = spi_en &
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write_in &
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access_in &
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~fifo_wait &
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(dstaddr_in[5:0]==`SPI_TX);
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assign wait_out = fifo_wait; // & tx_write;
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//epiphany mode works in msb or lsb mode
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//data mode up to 64 bits works in lsb mode
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//for msb transfer, use byte writes only
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assign tx_data[PW-1:0] = {{(40){1'b0}},
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srcaddr_in[AW-1:0],
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data_in[AW-1:0]};
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//##################################
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//# FIFO PACKET WRITE
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//##################################
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oh_par2ser #(.PW(PW),
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.SW(SW))
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oh_par2ser (// Outputs
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.dout (fifo_din[SW-1:0]),
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.access_out (fifo_wr),
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.wait_out (fifo_wait),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.din (tx_data[PW-1:0]),
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.shift (1'b1),
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.datasize (datasize[7:0]),
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.load (tx_write),
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.lsbfirst (1'b1),
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.fill (1'b0),
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.wait_in (fifo_prog_full)
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);
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//##################################
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//# FIFO
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//###################################
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oh_fifo_sync #(.DEPTH(DEPTH),
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.DW(SW))
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fifo(// Outputs
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.dout (fifo_dout[7:0]),
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.full (fifo_full),
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.prog_full (fifo_prog_full),
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.empty (fifo_empty),
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.rd_count (),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.din (fifo_din[7:0]),
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.wr_en (fifo_wr),
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.rd_en (fifo_read));
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endmodule // spi_master_fifo
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl" "../../emesh/hdl")
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// End:
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