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289024fd89
- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
103 lines
3.4 KiB
Verilog
103 lines
3.4 KiB
Verilog
//#############################################################################
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//# Purpose: SPI slave #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module spi_slave #( parameter UREGS = 13, // number of spi slave regs
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parameter AW = 32, // addresss width
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parameter PW = 104 // packet width
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)
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(
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//clk,reset, cfg
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input clk, // core clock
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input nreset, // async active low reset
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input hw_en, // block enbale pin
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output [511:0] spi_regs, // all registers for control
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output spi_irq, // interrupt
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//IO interface
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input sclk, // spi clock
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input mosi, // slave input
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input ss, // slave select
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output miso, // slave output
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// read request to core
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output access_out, // valid transaction
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output [PW-1:0] packet_out, // data to core (from spi port)
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input wait_in, // pushback from core (not implemented)
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// return from core
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input access_in, // read response from core
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input [PW-1:0] packet_in, // read response packet from core
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output wait_out // pushback (not used)
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);
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//###############
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//# LOCAL WIRES
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//###############
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire cpha; // From spi_slave_regs of spi_slave_regs.v
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wire cpol; // From spi_slave_regs of spi_slave_regs.v
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wire irq_en; // From spi_slave_regs of spi_slave_regs.v
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wire lsbfirst; // From spi_slave_regs of spi_slave_regs.v
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wire [5:0] spi_addr; // From spi_slave_io of spi_slave_io.v
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wire spi_clk; // From spi_slave_io of spi_slave_io.v
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wire spi_en; // From spi_slave_regs of spi_slave_regs.v
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wire [7:0] spi_rdata; // From spi_slave_regs of spi_slave_regs.v, ...
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wire [7:0] spi_wdata; // From spi_slave_io of spi_slave_io.v
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wire spi_write; // From spi_slave_io of spi_slave_io.v
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// End of automatics
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spi_slave_regs #(.AW(AW),
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.PW(PW),
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.UREGS(UREGS))
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spi_slave_regs (/*AUTOINST*/
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// Outputs
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.spi_rdata (spi_rdata[7:0]),
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.spi_en (spi_en),
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.cpol (cpol),
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.cpha (cpha),
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.lsbfirst (lsbfirst),
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.irq_en (irq_en),
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.spi_regs (spi_regs[511:0]),
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.wait_out (wait_out),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.hw_en (hw_en),
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.spi_clk (spi_clk),
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.spi_wdata (spi_wdata[7:0]),
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.spi_write (spi_write),
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.spi_addr (spi_addr[5:0]),
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.access_out (access_out),
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.access_in (access_in),
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.packet_in (packet_in[PW-1:0]));
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spi_slave_io #(.PW(PW))
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spi_slave_io (/*AUTOINST*/
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// Outputs
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.miso (miso),
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.spi_clk (spi_clk),
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.spi_write (spi_write),
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.spi_addr (spi_addr[5:0]),
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.spi_wdata (spi_wdata[7:0]),
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.spi_rdata (spi_rdata[7:0]),
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.access_out (access_out),
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.sclk (sclk),
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.mosi (mosi),
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.ss (ss),
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.spi_en (spi_en),
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.cpol (cpol),
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.cpha (cpha),
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.lsbfirst (lsbfirst),
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.clk (clk),
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.nreset (nreset),
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.wait_in (wait_in));
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endmodule // spi_slave
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