mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-17 20:02:53 +08:00
a68bba1572
- Removed the cfgif block, too confusing. There is a good lesson here. Probably the n'th time I that I have been overzealous about reuse. When you end up adding a parameter to a block that duplicates the logic 2X it's always better to create two separate blocks... - Changed the register access interface to packet format - Change the priority on the etx_arbiter to pick read responses first - Removed redundant signals - Took away the read resonse bypass on remap in tx for now.. - Removed defparams (convention) - Unified wait signal on tx - Fixed cfg wait -
45 lines
1.1 KiB
Verilog
45 lines
1.1 KiB
Verilog
module edma (/*AUTOARG*/
|
|
// Outputs
|
|
reg_rdata, access_out, packet_out,
|
|
// Inputs
|
|
nreset, clk, reg_access, reg_packet, wait_in
|
|
);
|
|
|
|
/******************************/
|
|
/*Compile Time Parameters */
|
|
/******************************/
|
|
parameter RFAW = 6;
|
|
parameter AW = 32;
|
|
parameter DW = 32;
|
|
parameter PW = 104;
|
|
|
|
/******************************/
|
|
/*HARDWARE RESET (EXTERNAL) */
|
|
/******************************/
|
|
input nreset; //async reset
|
|
input clk;
|
|
|
|
/*****************************/
|
|
/*REGISTER INTERFACE */
|
|
/*****************************/
|
|
input reg_access;
|
|
input [PW-1:0] reg_packet;
|
|
output [31:0] reg_rdata;
|
|
|
|
/*****************************/
|
|
/*DMA TRANSACTION */
|
|
/*****************************/
|
|
output access_out;
|
|
output [PW-1:0] packet_out;
|
|
input wait_in;
|
|
|
|
//Tieoffs for now
|
|
assign access_out = 'b0;
|
|
assign packet_out = 'd0;
|
|
|
|
endmodule // edma
|
|
// Local Variables:
|
|
// verilog-library-directories:("." "../../common/hdl")
|
|
// End:
|
|
|