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35 lines
541 B
Verilog
35 lines
541 B
Verilog
module BUFR (/*AUTOARG*/
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// Outputs
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O,
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// Inputs
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I, CE, CLR
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);
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parameter BUFR_DIVIDE=4;
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parameter SIM_DEVICE=0;
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input I;
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input CE;
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input CLR;
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output O;
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//assign O=I & CE & ~CLR;
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//TODO: need to paraemtrize this!!!
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clock_divider clock_divider (
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// Outputs
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.clkout (O),
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.clkout90 (),
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// Inputs
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.clkin (I),
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.divcfg (4'b0010),//div4
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.reset (CLR)
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);
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endmodule // IBUFDS
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// Local Variables:
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// verilog-library-directories:("../../common/hdl")
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// End:
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