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96 lines
3.3 KiB
Verilog
96 lines
3.3 KiB
Verilog
//#############################################################################
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//# Purpose: MIO Transmit Datapath #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module mtx # ( parameter PW = 104, // fifo width
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parameter AW = 32, // fifo width
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parameter IOW = 8, // I./O data width
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parameter FIFO_DEPTH = 16, // fifo depth
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parameter TARGET = "GENERIC" // fifo target
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)
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(// reset, clk, cfg
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input clk, // main core clock
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input io_clk, // clock for tx logic
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input nreset, // async active low reset
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input tx_en, // transmit enable
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input ddr_mode, // configure mio in ddr mode
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input lsbfirst, // send bits lsb first
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input emode, //emesh mode
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input [1:0] iowidth,//input width
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// status
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output tx_empty, // tx fifo is empty
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output tx_full, // tx fifo is full (should never happen!)
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output tx_prog_full,// tx is getting full (stop sending!)
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// data to transmit
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input access_in, // fifo data valid
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input [PW-1:0] packet_in, // fifo packet
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output wait_out, // wait pushback for fifo
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// IO interface (90 deg clock supplied outside this block)
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output tx_access, // access signal for IO
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output [IOW-1:0] tx_packet, // packet for IO
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input tx_wait // pushback from IO
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);
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//###############
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//# LOCAL WIRES
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//###############
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [63:0] io_packet; // From mtx_fifo of mtx_fifo.v
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wire [7:0] io_valid; // From mtx_fifo of mtx_fifo.v
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wire io_wait; // From mtx_io of mtx_io.v
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// End of automatics
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//########################################
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//# Synchronization FIFO
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//########################################
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mtx_fifo #(.PW(PW),
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.AW(AW),
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.FIFO_DEPTH(FIFO_DEPTH),
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.TARGET(TARGET))
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mtx_fifo (/*AUTOINST*/
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// Outputs
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.wait_out (wait_out),
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.io_packet (io_packet[63:0]),
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.io_valid (io_valid[7:0]),
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// Inputs
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.clk (clk),
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.io_clk (io_clk),
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.nreset (nreset),
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.tx_en (tx_en),
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.emode (emode),
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.access_in (access_in),
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.packet_in (packet_in[PW-1:0]),
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.io_wait (io_wait));
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//########################################
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//# IO Logic (DDR, shift register)
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//########################################
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mtx_io #(.IOW(IOW))
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mtx_io (/*AUTOINST*/
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// Outputs
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.tx_packet (tx_packet[IOW-1:0]),
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.tx_access (tx_access),
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.io_wait (io_wait),
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// Inputs
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.nreset (nreset),
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.io_clk (io_clk),
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.ddr_mode (ddr_mode),
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.iowidth (iowidth[1:0]),
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.tx_wait (tx_wait),
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.io_valid (io_valid[7:0]),
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.io_packet (io_packet[IOW-1:0]));
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endmodule // mtx
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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