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oh/elink/hdl
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Andreas Olofsson 81db0b7582 Completing elink hierarchy change 
-splits out clock domains
-makes the core portion a clean/reusable module with defined interface
2015-05-10 23:38:08 -04:00
..
axi_elink.v
Adding elink with axi interfaces
2015-05-09 08:52:55 -04:00
ecfg_clocks.v
Moving chipid back to clocks
2015-05-10 23:35:41 -04:00
ecfg_if.v
Adding emesh as basic building block
2015-05-05 21:38:41 -04:00
eclocks.v
Cleanup
2015-05-09 08:57:49 -04:00
elink_constants.v
Using fifo_cdc instead of fifo_async
2015-05-07 23:45:36 -04:00
elink_example.v
Cleanup
2015-05-09 08:57:49 -04:00
elink_regmap.v
MILESTONE: register read/write working!
2015-05-04 10:49:17 -04:00
elink.v
Completing elink hierarchy change
2015-05-10 23:38:08 -04:00
emaxi.v
Cleaning up logic to fit new access/packet interface
2015-05-09 08:56:51 -04:00
ereset.v
Cleanup
2015-05-01 17:31:45 -04:00
erx_cfg.v
Renaming for my sanity (etx/erx split)
2015-05-05 14:56:35 -04:00
erx_core.v
Completing elink hierarchy change
2015-05-10 23:38:08 -04:00
erx_disty.v
Completing elink hierarchy change
2015-05-10 23:38:08 -04:00
erx_fifo.v
Completing elink hierarchy change
2015-05-10 23:38:08 -04:00
erx_io.v
Completing elink hierarchy change
2015-05-10 23:38:08 -04:00
erx_protocol.v
Completing elink hierarchy change
2015-05-10 23:38:08 -04:00
erx_remap.v
Completing elink hierarchy change
2015-05-10 23:38:08 -04:00
erx_timer.v
Adding timeout circuit
2015-04-27 16:02:15 -04:00
erx.v
Completing elink hierarchy change
2015-05-10 23:38:08 -04:00
esaxi.v
Cleaning up logic to fit new access/packet interface
2015-05-09 08:56:51 -04:00
etx_arbiter.v
Completing elink hierarchy change
2015-05-10 23:38:08 -04:00
etx_cfg.v
Completing elink hierarchy change
2015-05-10 23:38:08 -04:00
etx_core.v
Adding etx/erx core modules
2015-05-10 23:06:52 -04:00
etx_fifo.v
Completing elink hierarchy change
2015-05-10 23:38:08 -04:00
etx_io.v
MILESTONE: Read/write works back and forth
2015-05-04 17:13:51 -04:00
etx_protocol.v
Removing testmode, bad idea
2015-05-10 23:35:04 -04:00
etx_remap.v
Separate rd/wr stalls
2015-05-04 17:09:50 -04:00
etx.v
Completing elink hierarchy change
2015-05-10 23:38:08 -04:00