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22714f3d9d
* Adding an improved monitor file * Adding mesh interface (avoids crud logic at top level) * A emesh packet memory module
68 lines
1.7 KiB
Verilog
68 lines
1.7 KiB
Verilog
module emesh_monitor(/*AUTOARG*/
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// Inputs
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clk, nreset, dut_access, dut_packet, wait_in, coreid
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);
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parameter PW = 104;
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parameter IDW = 12;
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parameter INDEX = 0;
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parameter NAME = "not_declared";
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//clock and reset
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input clk;
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input nreset;
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//monitors transaction on the wire
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input dut_access;
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input [PW-1:0] dut_packet;
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input wait_in;
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input [IDW-1:0] coreid;
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//core name for trace
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reg [31:0] ftrace;
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reg [255:0] tracefile;
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//Dumps into
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initial
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begin
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//TODO: Figure out these delays
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#10
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//index should be core ID
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$sformat(tracefile,"%0s_%0h%s",NAME,coreid,".trace");
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ftrace = $fopen({tracefile}, "w");
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end
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always @ (posedge clk or negedge nreset)
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if(nreset & dut_access & ~wait_in)
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$fwrite(ftrace, "%h_%h_%h_%h\n",dut_packet[PW-1:72],dut_packet[71:40],dut_packet[39:8],dut_packet[7:0]);
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endmodule // dut_monitor
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/*
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Copyright (C) 2015 Adapteva, Inc.
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Contributed by Andreas Olofsson <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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