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oh/stdlib/testbench
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aolofsson 822fa009b8 Refactoring simulation control file 
- Better names (clk1/clk2 was confusing)
- Removing supplies (rare special case), handle with ctrl
- Remove sting passing parameters for testname, primitive, not useuful
2022-06-24 22:17:42 -04:00
..
tests
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cfg_random.v
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dut_clockdiv.v
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dut_debouncer.v
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dut_fifo_generic.v
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dut_gray.v
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dut_template.v
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dv_driver.v
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dv_random.v
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dv_stimulus.v
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dv_top.v
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firmware_example.hex
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libs.cmd
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oh_simchecker.v
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oh_simctrl.v
Refactoring simulation control file
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oh.gtkw
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README.md
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run.sh
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stimulus.v
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tb_dut.v
Adding stub file for tb_dut wrapper
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tb_oh_pulse.v
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tb_oh_random.v
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tb_oh_stimulus.v
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test.mem
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timescale.v
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README.md

What defines are used

iverilog -g2005 -DTARGET_SIM=1 $cfg $core.v $DV -f $LIBS -o $core.bin

How to compile all duts?

The script "build_all.sh" builds all dut files in this directory with random

./build_all.sh