Andreas Olofsson 842a6d894a Fixing enable/reset: ...

-Removing enable from ISERDES, not healthy
-Moving all logic to protocol block. (this is an IO block)
-Removing tow redundant pipeline stages (check this??)

2015-04-23 18:01:19 -04:00

..

ecfg_if.v

Splitting register file (rx,tx,base)

2015-04-23 17:50:45 -04:00

ecfg_rx.v

Splitting register file (rx,tx,base)

2015-04-23 17:50:45 -04:00

ecfg_tx.v

Splitting register file (rx,tx,base)

2015-04-23 17:50:45 -04:00

ecfg.v

Message box working...

2015-04-19 21:55:07 -04:00

eclocks.v

Clarified lclk names

2015-04-22 15:03:24 -04:00

elink_constants.v

Renaming constants file

2015-04-22 13:56:48 -04:00

elink_regmap.v

Message box working...

2015-04-19 21:55:07 -04:00

elink.v

Clarified lclk names

2015-04-22 15:03:24 -04:00

emaxi.v

Bug fix, missing pipeline stage on read response

2015-04-21 17:14:30 -04:00

ememory.v

Implemented enesh memory

2015-04-21 17:13:09 -04:00

ereset.v

Cleanup

2015-04-18 16:26:32 -04:00

erx_disty.v

MILESTONE: Open souce simulation elink loopback working!

2015-04-17 15:51:55 -04:00

erx_io.v

Fixing enable/reset:

2015-04-23 18:01:19 -04:00

erx_protocol.v

Cleanup

2015-04-23 17:59:36 -04:00

erx.v

Cleanup

2015-04-18 16:26:32 -04:00

esaxi.v

Milestone: WRITE AND READ FROM HOST WORKS!

2015-04-21 17:16:20 -04:00

etx_arbiter.v

Packet interface change

2015-04-23 17:57:24 -04:00

etx_io.v

Clarified lclk names

2015-04-22 15:03:24 -04:00

etx_protocol.v

Packet interface change

2015-04-23 17:56:15 -04:00

etx.v

Major upgrade

2015-04-23 17:58:18 -04:00