mirror of
https://github.com/aolofsson/oh.git
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233 lines
7.5 KiB
Verilog
233 lines
7.5 KiB
Verilog
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//#########################################################################
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//# GPIO (Supports up to 32 GPIO pins)
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//# -each pin can be an output or input
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//# -level and edge interrupts supported on every input pin
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//#########################################################################
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`include "gpio_regmap.v"
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module gpio(/*AUTOARG*/
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// Outputs
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reg_rdata, gpio_out, gpio_en, gpio_irq, gpio_ilat,
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// Inputs
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nreset, clk, reg_access, reg_packet, gpio_in
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);
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//##################################################################
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//# INTERFACE
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//##################################################################
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parameter N = 24; // number of gpio pins
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parameter AW = 32; // address width
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parameter PW = 2*AW+40; // packet width
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parameter ID = 0; // block id to match to, bits [10:8]
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//clk, reset
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input nreset; // asynchronous active low reset
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input clk; // clock
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//register access interface
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input reg_access; // register access (read only)
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input [PW-1:0] reg_packet; // data/address
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output [31:0] reg_rdata; // readback data
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//IO signals
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output [N-1:0] gpio_out; // data to drive to IO pins
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output [N-1:0] gpio_en; // tristate enables for IO pins
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input [N-1:0] gpio_in; // data from IO pins
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//global interrupt
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output gpio_irq; // or of all interrupts
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output [31:0] gpio_ilat; // individual interrupt outputs
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//##################################################################
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//# BODY
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//##################################################################
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//registers
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reg [N-1:0] odata_reg;
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reg [N-1:0] oen_reg;
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reg [N-1:0] idata_reg;
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reg [N-1:0] itype_reg;
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reg [N-1:0] ipol_reg;
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reg [N-1:0] imask_reg;
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reg [N-1:0] ilat_reg;
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reg [N-1:0] gpio_reg;
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reg [AW-1:0] reg_rdata;
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//nets
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reg [N-1:0] ilat_in;
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reg [N-1:0] ilat_event;
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wire [N-1:0] gpio_sync;
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wire [N-1:0] event_posedge;
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wire [N-1:0] event_negedge;
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integer i,j;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] data_in; // From p2e of packet2emesh.v
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wire [1:0] datamode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
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wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
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wire write_in; // From p2e of packet2emesh.v
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// End of automatics
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//################################
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//# SYNCHRONIZE INPUT DATA
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//################################
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oh_dsync #(.DW(N))
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dsync (.dout (gpio_sync[N-1:0]),
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.clk (clk),
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.din (gpio_in[N-1:0]));
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//################################
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//# REGISTER ACCESS DECODE
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//################################
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packet2emesh p2e(.packet_in (reg_packet[PW-1:0]),
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/*AUTOINST*/
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// Outputs
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.write_in (write_in),
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.datamode_in (datamode_in[1:0]),
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.ctrlmode_in (ctrlmode_in[4:0]),
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.dstaddr_in (dstaddr_in[AW-1:0]),
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.srcaddr_in (srcaddr_in[AW-1:0]),
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.data_in (data_in[AW-1:0]));
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assign gpio_match = reg_access &
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(dstaddr_in[10:8]==ID);
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assign gpio_write = gpio_match & write_in;
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assign gpio_read = gpio_match & ~write_in;
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assign odata_write = gpio_write & (dstaddr_in[7:2]==`GPIO_ODATA);
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assign odataand_write = gpio_write & (dstaddr_in[7:2]==`GPIO_ODATAAND);
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assign odataorr_write = gpio_write & (dstaddr_in[7:2]==`GPIO_ODATAORR);
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assign odataxor_write = gpio_write & (dstaddr_in[7:2]==`GPIO_ODATAXOR);
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assign oen_write = gpio_write & (dstaddr_in[7:2]==`GPIO_OEN);
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assign idata_write = gpio_write & (dstaddr_in[7:2]==`GPIO_IDATA);
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assign itype_write = gpio_write & (dstaddr_in[7:2]==`GPIO_ITYPE);
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assign ipol_write = gpio_write & (dstaddr_in[7:2]==`GPIO_IPOL);
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assign imask_write = gpio_write & (dstaddr_in[7:2]==`GPIO_IMASK);
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assign imaskand_write = gpio_write & (dstaddr_in[7:2]==`GPIO_IMASKAND);
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assign imaskorr_write = gpio_write & (dstaddr_in[7:2]==`GPIO_IMASKORR);
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assign ilat_write = gpio_write & (dstaddr_in[7:2]==`GPIO_ILAT);
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assign ilatand_write = gpio_write & (dstaddr_in[7:2]==`GPIO_ILATAND);
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//################################
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//# OUTPUT CONTROL REGISTERS
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//################################
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//ODATA
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always @ (posedge clk)
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if(odata_write)
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odata_reg[N-1:0] <= data_in[N-1:0];
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else if(odataand_write)
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odata_reg[N-1:0] <= data_in[N-1:0] & odata_reg[N-1:0];
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else if(odataorr_write)
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odata_reg[N-1:0] <= data_in[N-1:0] | odata_reg[N-1:0];
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assign gpio_out[N-1:0] = odata_reg[N-1:0];
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//OEN
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always @ (posedge clk)
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if(oen_write)
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oen_reg[N-1:0] <= data_in[N-1:0];
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assign gpio_en[N-1:0] = oen_reg[N-1:0];
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//################################
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//# INPUT CONTROL REGISTERS
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//################################
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//IDATA
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always @ (posedge clk)
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idata_reg[N-1:0] <= gpio_sync[N-1:0];
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//ITYPE
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//0=level
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//1=edge
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always @ (posedge clk)
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if(itype_write)
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itype_reg[N-1:0] <= data_in[N-1:0];
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//IPOLARITY
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//0=positive
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//1=negative
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always @ (posedge clk)
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if(ipol_write)
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ipol_reg[N-1:0] <= data_in[N-1:0];
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//IMASK
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always @ (posedge clk)
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if(imask_write)
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imask_reg[N-1:0] <= data_in[N-1:0];
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else if(imaskand_write)
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imask_reg[N-1:0] <= imask_reg[N-1:0] & data_in[N-1:0];
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else if(imaskorr_write)
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imask_reg[N-1:0] <= imask_reg[N-1:0] | data_in[N-1:0];
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//ILAT
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always @ (posedge clk or negedge nreset)
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if(~nreset)
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ilat_reg[N-1:0] <= 'b0;
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else
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ilat_reg[N-1:0] <= ilat_in[N-1:0];
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//################################
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//# INTERRUPT CONTROL
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//################################
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//ILAT
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always @*
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for(i=0;i<N;i=i+1)
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ilat_in[i] =(ilat_write & data_in[i]) | // ilat set
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(ilat_reg[i] & ~(ilatand_write & ~data_in[i]))|// ilat clear
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(ilat_event[i]); // event
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//shadow
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always @ (posedge clk)
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gpio_reg[N-1:0] <= gpio_sync[N-1:0];
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//events
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assign event_posedge[N-1:0] = gpio_sync[N-1:0] & ~gpio_reg[N-1:0];
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assign event_negedge[N-1:0] = ~gpio_sync[N-1:0] & gpio_reg[N-1:0];
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always @*
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for(j=0;j<N;j=j+1)
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ilat_event[j] = (~itype_reg[j] & ~ipol_reg[j] & gpio_sync[j]) |
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(~itype_reg[j] & ipol_reg[j] & ~gpio_sync[j]) |
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(itype_reg[j] & ~ipol_reg[j] & event_posedge[j]) |
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(itype_reg[j] & ipol_reg[j] & event_negedge[j]);
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//global interrupt output
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assign gpio_irq = |ilat_reg[N-1:0];
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//################################
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//# READBACK
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//################################
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always @ (posedge clk)
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if(gpio_read)
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case(dstaddr_in[7:2])
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`GPIO_OEN : reg_rdata[31:0] <= oen_reg[N-1:0];
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`GPIO_IDATA : reg_rdata[31:0] <= idata_reg[N-1:0];
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`GPIO_ITYPE : reg_rdata[31:0] <= itype_reg[N-1:0];
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`GPIO_IPOL : reg_rdata[31:0] <= ipol_reg[N-1:0];
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`GPIO_IMASK : reg_rdata[31:0] <= imask_reg[N-1:0];
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`GPIO_ILAT : reg_rdata[31:0] <= ilat_reg[N-1:0];
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default : reg_rdata[AW-1:0] <='b0;
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endcase // case (dstaddr_in[7:2])
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endmodule // gpio
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
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// End:
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