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8461277ab1
-There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect! -Configuration can be done from host through txwr/txrd path of any register -The RX IO pins can only access the RX side of the design
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OH!
Open Hardware (Pure and Simple)
(work in progress...)