Ola Jeppsson feffddb166 GPIO: Update FPGA project to use parallella_gpio as top ...

Use parallella_base pin constraints.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>

2016-04-29 18:03:41 +02:00

..

accelerator

Reorg! Why?

2016-03-22 08:13:40 -04:00

aes

Reorg! Why?

2016-03-22 08:13:40 -04:00

axi

Reorg! Why?

2016-03-22 08:13:40 -04:00

chip

Fixing readme

2016-04-15 22:38:06 -04:00

common

common: Add oh_tristate module

2016-04-29 18:01:20 +02:00

edma

Fixing more synthesis warnings

2016-04-17 10:37:08 -04:00

elink

Fixing oh_dsync instantiation

2016-04-13 20:54:12 -04:00

emailbox

Reorg! Why?

2016-03-22 08:13:40 -04:00

emesh

Fixing memory macro instantiation

2016-04-05 22:43:29 -04:00

emmu

Using DEPTH as specifier for memory

2016-04-14 10:29:49 -04:00

etrace

Reorg! Why?

2016-03-22 08:13:40 -04:00

gpio

GPIO: Update FPGA project to use parallella_gpio as top

2016-04-29 18:03:41 +02:00

mio

Vivado doesn't like localparam / clog2 combo

2016-04-14 21:46:14 +02:00

parallella

Merge branch 'stable-prepared' into merge-stable

2016-04-14 20:41:47 +02:00

pic

Making interrupt 0 non-maskable.

2016-04-11 20:36:58 -04:00

risc-v

Reorg! Why?

2016-03-22 08:13:40 -04:00

spi

Vivado doesn't like localparam / clog2 combo

2016-04-14 21:46:14 +02:00

xilibs

Reorg! Why?

2016-03-22 08:13:40 -04:00