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64 lines
4.6 KiB
Markdown
64 lines
4.6 KiB
Markdown
Common Module Library
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===============================================
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| Name |Done| Function |
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| [oh_8b10b_decode](hdl/oh_8b10b_decode.v) | N | 8b10b decoder |
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| [oh_8b10b_encode](hdl/oh_8b10b_encode.v) | N | 8b10b encoder |
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| [oh_abs](hdl/oh_abs.v) | Y | Absolute value calculator |
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| [oh_add](hdl/oh_add.v) | Y | Binary adder |
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| [oh_arbiter](hdl/oh_arbiter.v) | Y | Configurable arbiter |
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| [oh_bin2gray](hdl/oh_bin2gray.v) | Y | Binary to gray converter |
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| [oh_bitreverse](hdl/oh_bitreverse.v) | Y | Bitreverse circuit |
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| [oh_clockdiv](hdl/oh_clockdiv.v) | Y | Combinatorial clock divider |
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| [oh_clockgate](hdl/oh_clockgate.v) | Y | Clock gater |
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| [oh_counter](hdl/oh_counter.v) | Y | Binary counter |
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| [oh_crc](hdl/oh_crc.v) | Y | CRC encoder |
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| [oh_csa32](hdl/oh_csa32.v) | Y | Carry save adder 3:2 |
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| [oh_csa42](hdl/oh_csa42.v) | Y | Carry save adder 4:2 |
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| [oh_csa62](hdl/oh_csa62.v) | Y | Carry save adder 6:2 |
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| [oh_csa92](hdl/oh_csa92.v) | Y | Carry save adder 9:2 |
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| [oh_datagate](hdl/oh_datagate.v) | Y | Data gater |
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| [oh_debouncer](hdl/oh_debouncer.v) | Y | Button debouncer |
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| [oh_dsync](hdl/oh_dsync.v) | Y | Data synchronizizer |
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| [oh_edge2pulse](hdl/oh_edge2pulse.v) | Y | Converts edge to pulse |
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| [oh_edgealign](hdl/oh_edgealign.v) | Y | Fast/slow clock alignment |
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| [oh_edgedetect](hdl/oh_edgedetect.v) | Y | Configurable edge detector |
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| [oh_fall2pulse](hdl/oh_fall2pulse.v) | Y | Converts falling edge to pulse |
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| [oh_fifo_async](hdl/oh_fifo_async.v) | Y | Asynchonous FIFO (dual clock) |
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| [oh_fifo_cdc](hdl/oh_fifo_cdc.v) | Y | Clock domain crossing FIFO |
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| [oh_fifo_generic](hdl/oh_fifo_generic.v) | Y | Generic synchronous FIFO |
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| [oh_fifo_sync](hdl/oh_fifo_sync.v) | Y | Synchronous FIFO |
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| [oh_gray2bin](hdl/oh_gray2bin.v) | Y | Gray to binary converter |
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| [oh_iddr](hdl/oh_iddr.v) | Y | Dual data rate input buffer |
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| [oh_lat0](hdl/oh_lat0.v) | Y | Latch on low clock |
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| [oh_lat1](hdl/oh_lat1.v) | Y | latch on high clock |
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| [oh_memory_dp](hdl/oh_memory_dp.v) | Y | Dual ported memory |
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| [oh_memory_sp](hdl/oh_memory_sp.v) | Y | Single ported memory |
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| [oh_mux12](hdl/oh_mux12.v) | Y | Twelve port mux |
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| [oh_mux2](hdl/oh_mux2.v) | Y | Two port mux |
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| [oh_mux3](hdl/oh_mux3.v) | Y | Three port mux |
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| [oh_mux4](hdl/oh_mux4.v) | Y | Four port mux |
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| [oh_mux5](hdl/oh_mux5.v) | Y | Five port mux |
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| [oh_mux6](hdl/oh_mux6.v) | Y | Six port mux |
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| [oh_mux7](hdl/oh_mux7.v) | Y | Seven port mux |
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| [oh_mux8](hdl/oh_mux8.v) | Y | Eight port mux |
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| [oh_mux9](hdl/oh_mux9.v) | Y | Ten port mux |
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| [oh_mux](hdl/oh_mux.v) | Y | Generic n-port mux |
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| [oh_oddr](hdl/oh_oddr.v) | Y | Dual data rate output buffer |
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| [oh_par2ser](hdl/oh_par2ser.v) | Y | Parallel to serial converter |
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| [oh_parity](hdl/oh_parity.v) | Y | Parity calculator |
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| [oh_pulse2pulse](hdl/oh_pulse2pulse.v) | Y | Pulse to pulse CDC circuit |
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| [oh_rise2pulse](hdl/oh_rise2pulse.v) | Y | Rising edge to pulse converter |
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| [oh_rsync](hdl/oh_rsync.v) | Y | Reset synchronzation circuit |
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| [oh_ser2par](hdl/oh_ser2par.v) | Y | Serial to parallel converter |
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| [oh_shifter](hdl/oh_shifter.v) | Y | Bit shifter |
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| [oh_standby](hdl/oh_standby.v) | Y | Standby circuit |
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| [oh_stretcher](hdl/oh_stretcher.v) | Y | Pulse stretcher |
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