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117 lines
3.5 KiB
Verilog
117 lines
3.5 KiB
Verilog
//#############################################################################
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//# Function: Synchronous FIFO #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_fifo_sync #(parameter DW = 104, //FIFO width
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parameter DEPTH = 32, //FIFO depth
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parameter REG = 1, //Register fifo output
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parameter PROG_FULL = DEPTH-1, //prog_full threshold
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parameter AW = $clog2(DEPTH), //rd_count width
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parameter DUMPVAR = 1 // dump array
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)
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(
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input clk, // clock
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input nreset, //async reset
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input clear, //clears reset (synchronous signal)
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input [DW-1:0] din, // data to write
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input wr_en, // write fifo
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input rd_en, // read fifo
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output [DW-1:0] dout, // output data (next cycle)
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output full, // fifo full
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output prog_full, // fifo is almost full
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output empty, // fifo is empty
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output reg [AW-1:0] rd_count // valid entries in fifo
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);
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reg [AW:0] wr_addr;
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reg [AW:0] rd_addr;
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wire fifo_read;
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wire fifo_write;
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assign fifo_read = rd_en & ~empty;
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assign fifo_write = wr_en & ~full;
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assign prog_full = (rd_count[AW-1:0] == PROG_FULL);
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assign ptr_match = (wr_addr[AW-1:0] == rd_addr[AW-1:0]);
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assign full = ptr_match & (wr_addr[AW]==!rd_addr[AW]);
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assign fifo_empty = ptr_match & (wr_addr[AW]==rd_addr[AW]);
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always @ (posedge clk or negedge nreset)
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if(~nreset)
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begin
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wr_addr[AW:0] <= 'd0;
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rd_addr[AW:0] <= 'b0;
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rd_count[AW:0] <= 'b0;
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end
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else if(clear)
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begin
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wr_addr[AW:0] <= 'd0;
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rd_addr[AW:0] <= 'b0;
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rd_count[AW:0] <= 'b0;
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end
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else if(fifo_write & fifo_read)
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begin
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wr_addr[AW:0] <= wr_addr[AW:0] + 'd1;
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rd_addr[AW:0] <= rd_addr[AW:0] + 'd1;
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end
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else if(fifo_write)
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begin
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wr_addr[AW:0] <= wr_addr[AW:0] + 'd1;
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rd_count[AW-1:0]<= rd_count[AW-1:0] + 'd1;
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end
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else if(fifo_read)
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begin
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rd_addr[AW:0] <= rd_addr[AW:0] + 'd1;
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rd_count[AW-1:0]<= rd_count[AW-1:0] - 'd1;
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end
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//Empty register to account for RAM output register
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generate
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if(REG)
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begin
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reg empty_reg;
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always @ (posedge clk)
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empty_reg <= fifo_empty;
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assign empty = empty_reg;
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end
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else
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assign empty = fifo_empty;
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endgenerate
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// GENERIC DUAL PORTED MEMORY
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oh_memory_dp
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#(.DW(DW),
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.DEPTH(DEPTH),
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.DUMPVAR(DUMPVAR),
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.REG(REG))
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mem (// read port
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.rd_dout (dout[DW-1:0]),
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.rd_clk (clk),
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.rd_en (fifo_read),
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.rd_addr (rd_addr[AW-1:0]),
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// write port
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.wr_clk (clk),
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.wr_en (fifo_write),
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.wr_wem ({(DW){1'b1}}),
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.wr_addr (wr_addr[AW-1:0]),
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.wr_din (din[DW-1:0]));
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`ifdef TARGET_SIM
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assign rd_error = rd_en & empty;
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assign wr_error = wr_en & full;
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always @ (posedge rd_error)
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#1 if(rd_error)
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$display ("ERROR: Reading empty FIFO in %m at ",$time);
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always @ (posedge wr_error)
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#1 if(wr_error)
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$display ("ERROR: Writing full FIFO in %m at ",$time);
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`endif
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endmodule // oh_fifo_sync
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