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37 lines
1.0 KiB
Verilog
37 lines
1.0 KiB
Verilog
//#############################################################################
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//# Function: Gray to binary encoder #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_gray2bin #(parameter DW = 32) // width of data inputs
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(
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input [DW-1:0] in, //gray encoded input
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output [DW-1:0] out //binary encoded output
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);
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reg [DW-1:0] bin;
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wire [DW-1:0] gray;
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integer i,j;
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assign gray[DW-1:0] = in[DW-1:0];
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assign out[DW-1:0] = bin[DW-1:0];
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always @*
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begin
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bin[DW-1] = gray[DW-1];
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for (i=0; i<(DW-1); i=i+1)
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begin
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bin[i] = 1'b0;
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for (j=i; j<DW; j=j+1)
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bin[i] = bin[i] ^ gray [j];
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end
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end
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endmodule // oh_gray2bin
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