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9e9d323025
-Should be ifdef, since this is a global. You will never be doing and not an asic at the same time!
28 lines
1009 B
Verilog
28 lines
1009 B
Verilog
//#############################################################################
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//# Function: Achive high latch #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_lat1 #(parameter DW = 1 //data width
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)
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( input clk, // clk, latch when clk=1
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input [DW-1:0] in, // input data
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output [DW-1:0] out // output data (stable/latched when clk=0)
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);
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`ifdef CFG_ASIC
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asic_lat1 i_lat [DW-1:0] (.clk(clk),
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.in(in[DW-1:0]),
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.out(out[DW-1:0]));
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`else
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reg [DW-1:0] out_reg;
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always @ (clk or in)
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if (clk)
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out_reg[DW-1:0] <= in[DW-1:0];
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assign out[DW-1:0] = out_reg[DW-1:0];
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`endif
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endmodule // oh_lat1
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