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38 lines
1.2 KiB
Verilog
38 lines
1.2 KiB
Verilog
//#############################################################################
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//# Function: 4:1 one hot mux #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_mux4 #(parameter DW = 1 ) // width of mux
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(
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input sel3,
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input sel2,
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input sel1,
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input sel0,
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input [DW-1:0] in3,
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input [DW-1:0] in2,
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input [DW-1:0] in1,
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input [DW-1:0] in0,
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output [DW-1:0] out //selected data output
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);
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assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
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{(DW){sel1}} & in1[DW-1:0] |
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{(DW){sel2}} & in2[DW-1:0] |
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{(DW){sel3}} & in3[DW-1:0]);
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`ifdef TARGET_SIM
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wire error;
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assign error = (sel0 | sel1 | sel2 | sel3) &
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~(sel0 ^ sel1 ^ sel2 ^ sel3);
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always @ (posedge error)
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begin
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#1 if(error)
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$display ("ERROR at in oh_mux4 %m at ",$time);
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end
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`endif
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endmodule // oh_mux4
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