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33 lines
866 B
Verilog
33 lines
866 B
Verilog
/*
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* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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`timescale 1ns / 1ps
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module test_endian;
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reg [31:0] i;
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initial begin
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i = 32'h12345678; // big endian
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#100;
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$display("%h %h %h %h", i[31:24], i[23:16], i[15:8], i[7:0]);
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// 12 34 56 78
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$finish;
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end
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endmodule
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