Andreas Olofsson 852d7da490 Adding generic target ...

- all sims should have a "cfg file"
- since everything is configurable, this is the easiest way

2016-02-23 15:44:31 -05:00

..

cfg_generic.v

Adding generic target

2016-02-23 15:44:31 -05:00

oh_8b10b_decoder.v

Cleanup

2016-01-10 15:58:28 -05:00

oh_8b10b_encoder.v

Fixing silly compiler errors

2016-01-17 21:15:28 -05:00

oh_abs.v

Adding interfaces

2015-12-17 13:50:59 -05:00

oh_add.v

Adding interfaces

2015-12-17 13:50:59 -05:00

oh_arbiter.v

Fixing warning messages in chip synthesis tool

2016-02-12 11:04:52 -05:00

oh_bin2gray.v

Adding functionality for various modules

2016-01-10 13:33:31 -05:00

oh_clockdiv.v

Massive reorganization to impove reuse

2015-11-30 13:45:49 -05:00

oh_clockgate.v

Vectorizing oh_clockgate

2015-12-03 18:03:02 -05:00

oh_counter.v

Fixing basic counter

2016-02-23 15:41:35 -05:00

oh_crc.v

Fixing silly compiler errors

2016-01-17 21:15:28 -05:00

oh_csa32.v

Prettyfying csa port names

2015-12-03 18:01:47 -05:00

oh_csa42.v

Prettyfying csa port names

2015-12-03 18:01:47 -05:00

oh_csa62.v

Prettyfying csa port names

2015-12-03 18:01:47 -05:00

oh_csa92.v

Prettyfying csa port names

2015-12-03 18:01:47 -05:00

oh_datagate.v

Fixing warning messages in chip synthesis tool

2016-02-12 11:04:52 -05:00

oh_debouncer.v

Adding debouncer circuit

2016-02-23 15:41:18 -05:00

oh_dsync.v

Massive reorganization to impove reuse

2015-11-30 13:45:49 -05:00

oh_ecc_read.v

Adding interfaces

2015-12-17 13:50:59 -05:00

oh_edgealign.v

Massive reorganization to impove reuse

2015-11-30 13:45:49 -05:00

oh_fifo_async.v

Reorg: moving generic fifo to separate file

2016-02-23 15:43:28 -05:00

oh_fifo_cdc.v

Interface cleanups

2016-01-20 10:51:57 -05:00

oh_fifo_generic.v

Adding experimental fifo circuit

2016-02-23 15:42:55 -05:00

oh_fifo_sync.v

Adding rd_counter to sync fifo interface

2016-01-20 10:50:00 -05:00

oh_gray2bin.v

Adding functionality for various modules

2016-01-10 13:33:31 -05:00

oh_hamming_encoder.v

Cleanup

2016-01-10 15:58:28 -05:00

oh_iddr.v

Fixing new ddr circuits

2016-02-23 15:42:32 -05:00

oh_lat0.v

Fixing unconnected wire bug

2015-12-05 09:01:18 -05:00

oh_lat1.v

Fixing unconnected wire bug

2015-12-05 09:01:18 -05:00

oh_memory_dp.v

Changing dp memory interface in calling module

2016-01-11 17:34:35 -05:00

oh_memory_sp.v

Making single/dual port memory interfaces constistant

2016-01-11 15:06:22 -05:00

oh_mux2.v

Massive reorganization to impove reuse

2015-11-30 13:45:49 -05:00

oh_mux3.v

Massive reorganization to impove reuse

2015-11-30 13:45:49 -05:00

oh_mux4.v

Fixing warning messages in chip synthesis tool

2016-02-12 11:04:52 -05:00

oh_mux5.v

Massive reorganization to impove reuse

2015-11-30 13:45:49 -05:00

oh_mux6.v

Massive reorganization to impove reuse

2015-11-30 13:45:49 -05:00

oh_mux7.v

Massive reorganization to impove reuse

2015-11-30 13:45:49 -05:00

oh_mux8.v

Massive reorganization to impove reuse

2015-11-30 13:45:49 -05:00

oh_mux9.v

Massive reorganization to impove reuse

2015-11-30 13:45:49 -05:00

oh_mux12.v

Massive reorganization to impove reuse

2015-11-30 13:45:49 -05:00

oh_mux.v

Adding generic N:1 mux

2016-01-20 17:22:05 -05:00

oh_oddr.v

Fixing new ddr circuits

2016-02-23 15:42:32 -05:00

oh_par2ser.v

Adding functionality for various modules

2016-01-10 13:33:31 -05:00

oh_pulse2pulse.v

Massive reorganization to impove reuse

2015-11-30 13:45:49 -05:00

oh_rsync.v

Fixing warning messages in chip synthesis tool

2016-02-12 11:04:52 -05:00

oh_ser2par.v

Adding functionality for various modules

2016-01-10 13:33:31 -05:00

oh_shifter.v

Adding interfaces

2015-12-17 13:50:59 -05:00

oh_standby.v

Fixed unconnected wires in standby circuit

2015-12-04 17:32:15 -05:00

oh_stretcher.v

Massive reorganization to impove reuse

2015-11-30 13:45:49 -05:00