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69 lines
1.9 KiB
Verilog
69 lines
1.9 KiB
Verilog
//#########################################################################
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//# Function: A digital debounce circuit
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//# Usage: Set the BOUNCE and CLKPERIOD values during instantional to suite
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//# your switch and clkperiod.
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//#
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//########################################################################
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module oh_debouncer (/*AUTOARG*/
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// Outputs
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clean_out,
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// Inputs
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clk, nreset, noisy_in
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);
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// parameters (in milliseconds)
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parameter BOUNCE = 100; // bounce time of switch (s)
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parameter CLKPERIOD = 0.00001; // period (10ns=0.0001ms))
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parameter CW = $clog2(BOUNCE/CLKPERIOD);// counter width needed
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// signal interface
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input clk; // clock to synchronize to
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input nreset; // syncronous active high reset
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input noisy_in; // noisy input signal to filter
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output clean_out; // clean signal to logic
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//temp variables
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wire noisy_synced;
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reg noisy_reg;
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reg clean_out;
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wire nreset_synced;
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// synchronize reset
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oh_dsync dsync (.dout (noisy_synced),
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.clk (clk),
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.din (noisy_in));
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// synchronize input to clk (always!)
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oh_rsync rsync (.nrst_out (nreset_synced),
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.clk (clk),
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.nrst_in (nreset));
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// detecting change in state on input
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always @ (posedge clk)
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noisy_reg <= noisy_synced;
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assign change_detected = noisy_reg ^ noisy_synced;
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// synchronous counter
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oh_counter #(.DW(CW))
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oh_counter (// Outputs
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.count (),
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.carry (carry),
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.zero (),
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// Inputs
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.clk (clk),
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.in (1'b1),
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.en (~carry), //done if you reach carry
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.load (change_detected | ~nreset_synced),
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.load_data ({(CW){1'b0}})
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);
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// sample noisy signal safely
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always @ (posedge clk)
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if(carry)
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clean_out <= noisy_reg;
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endmodule
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