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d275406aa6
- holding rx in reset state until tx is done - removing reset from all pipeline registers - removing reset from oddr/iddr - the idea is to keep things quiet not to block in lots of places. The only real block needed is in the FIFO to keep "noise" from propagating past the link. The link should be kept in a safe reset state until the rx fram is stable and the clock is running so that the pipe can be cleaned out.
113 lines
3.1 KiB
Verilog
113 lines
3.1 KiB
Verilog
/*
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This block handles the autoincrement needed for bursting and detects
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read responses
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*/
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`include "elink_regmap.v"
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module erx_protocol (/*AUTOARG*/
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// Outputs
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erx_test_access, erx_test_data, erx_rdwr_access, erx_rr_access,
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erx_packet,
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// Inputs
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clk, test_mode, rx_packet, rx_burst, rx_access
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter ID = 12'h800; //link id
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// System reset input
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input clk;
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//test mode
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input test_mode; //block all traffic in test mode
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output erx_test_access;
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output [31:0] erx_test_data;
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// Parallel interface, 8 eLink bytes at a time
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input [PW-1:0] rx_packet;
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input rx_burst;
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input rx_access;
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// Output to MMU / filter
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output erx_rdwr_access;
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output erx_rr_access;
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output [PW-1:0] erx_packet;
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//wires
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reg [31:0] dstaddr_reg;
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wire [31:0] dstaddr_next;
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wire [31:0] dstaddr_mux;
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reg erx_rdwr_access;
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reg erx_rr_access;
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reg [PW-1:0] erx_packet;
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wire [11:0] myid;
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wire [31:0] rx_addr;
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wire read_response;
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reg erx_test_access;
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//parsing inputs
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assign myid[11:0] = ID;
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assign rx_addr[31:0] = rx_packet[39:8];
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//Address generator for bursting
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always @ (posedge clk)
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if(rx_access)
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dstaddr_reg[31:0] <= dstaddr_mux[31:0];
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assign dstaddr_next[31:0] = dstaddr_reg[31:0] + 4'b1000;
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assign dstaddr_mux[31:0] = rx_burst ? dstaddr_next[31:0] :
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rx_addr[31:0];
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//Read response detector
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assign read_response = (rx_addr[31:20] == myid[11:0]) &
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(rx_addr[19:16] == `EGROUP_RR);
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//Pipeline stage and decode
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always @ (posedge clk)
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begin
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//Write/read request
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erx_rdwr_access <= ~test_mode & rx_access & ~read_response;
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//Read response
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erx_rr_access <= ~test_mode & rx_access & read_response;
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//Test packet
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erx_test_access <= test_mode & rx_access & ~read_response;
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//Common packet
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erx_packet[PW-1:0] <= {rx_packet[PW-1:40],
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dstaddr_mux[31:0],
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rx_packet[7:0]
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};
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end
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//Testdata to write
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assign erx_test_data[31:0] = erx_packet[71:40];
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endmodule // erx_protocol
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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/*
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Copyright (C) 2015 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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