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https://github.com/aolofsson/oh.git
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d275406aa6
- holding rx in reset state until tx is done - removing reset from all pipeline registers - removing reset from oddr/iddr - the idea is to keep things quiet not to block in lots of places. The only real block needed is in the FIFO to keep "noise" from propagating past the link. The link should be kept in a safe reset state until the rx fram is stable and the clock is running so that the pipe can be cleaned out.
317 lines
11 KiB
Verilog
317 lines
11 KiB
Verilog
module etx_core(/*AUTOARG*/
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// Outputs
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tx_access, tx_burst, tx_packet, txrd_wait, txrr_wait, txwr_wait,
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etx_cfg_access, etx_cfg_packet,
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// Inputs
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reset, clk, tx_io_wait, tx_rd_wait, tx_wr_wait, txrd_access,
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txrd_packet, txrr_access, txrr_packet, txwr_access, txwr_packet,
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etx_cfg_wait
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter RFAW = 6;
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parameter ID = 12'h000;
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//Clocks,reset,config
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input reset;
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input clk;
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//IO interface
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output tx_access;
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output tx_burst;
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output [PW-1:0] tx_packet;
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input tx_io_wait;
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input tx_rd_wait;
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input tx_wr_wait;
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//TXRD
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input txrd_access;
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input [PW-1:0] txrd_packet;
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output txrd_wait;
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//TXRR
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input txrr_access;
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input [PW-1:0] txrr_packet;
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output txrr_wait;
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//TXWR
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input txwr_access;
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input [PW-1:0] txwr_packet;
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output txwr_wait;
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//Configuration Interface (for ERX)
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output etx_cfg_access;
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output [PW-1:0] etx_cfg_packet;
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input etx_cfg_wait;
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//for status?
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wire[15:0] tx_status;
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [3:0] ctrlmode; // From etx_cfg of etx_cfg.v
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wire ctrlmode_bypass; // From etx_cfg of etx_cfg.v
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wire emmu_access; // From etx_mmu of emmu.v
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wire [PW-1:0] emmu_packet; // From etx_mmu of emmu.v
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wire etx_access; // From etx_arbiter of etx_arbiter.v
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wire [PW-1:0] etx_packet; // From etx_arbiter of etx_arbiter.v
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wire etx_rd_wait; // From etx_protocol of etx_protocol.v
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wire etx_remap_access; // From etx_remap of etx_remap.v
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wire [PW-1:0] etx_remap_packet; // From etx_remap of etx_remap.v
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wire etx_rr; // From etx_arbiter of etx_arbiter.v
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wire etx_wr_wait; // From etx_protocol of etx_protocol.v
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wire [8:0] gpio_data; // From etx_cfg of etx_cfg.v
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wire gpio_enable; // From etx_cfg of etx_cfg.v
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wire [14:0] mi_addr; // From etx_cfgif of ecfg_if.v
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wire [DW-1:0] mi_cfg_dout; // From etx_cfg of etx_cfg.v
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wire mi_cfg_en; // From etx_cfgif of ecfg_if.v
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wire [63:0] mi_din; // From etx_cfgif of ecfg_if.v
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wire [DW-1:0] mi_mmu_dout; // From etx_mmu of emmu.v
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wire mi_mmu_en; // From etx_cfgif of ecfg_if.v
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wire mi_we; // From etx_cfgif of ecfg_if.v
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wire mmu_enable; // From etx_cfg of etx_cfg.v
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wire remap_enable; // From etx_cfg of etx_cfg.v
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wire tx_enable; // From etx_cfg of etx_cfg.v
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// End of automatics
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/************************************************************/
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/*ELINK TRANSMIT ARBITER */
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/************************************************************/
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defparam etx_arbiter.ID=ID;
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etx_arbiter etx_arbiter (
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/*AUTOINST*/
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// Outputs
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.txwr_wait (txwr_wait),
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.txrd_wait (txrd_wait),
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.txrr_wait (txrr_wait),
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.etx_access (etx_access),
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.etx_packet (etx_packet[PW-1:0]),
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.etx_rr (etx_rr),
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// Inputs
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.clk (clk),
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.reset (reset),
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.txwr_access (txwr_access),
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.txwr_packet (txwr_packet[PW-1:0]),
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.txrd_access (txrd_access),
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.txrd_packet (txrd_packet[PW-1:0]),
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]),
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.etx_rd_wait (etx_rd_wait),
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.etx_wr_wait (etx_wr_wait),
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.etx_cfg_wait (etx_cfg_wait),
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.ctrlmode_bypass (ctrlmode_bypass),
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.ctrlmode (ctrlmode[3:0]));
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/************************************************************/
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/* CONFIGURATOIN PACKET */
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/************************************************************/
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/*ecfg_if AUTO_TEMPLATE (
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.\(.*\)_in (etx_\1[]),
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.\(.*\)_out (etx_cfg_\1[]),
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.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}),
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.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}),
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.wait_in (etx_cfg_wait),
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);
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*/
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defparam etx_cfgif.RX =0;
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ecfg_if etx_cfgif (.mi_dout3 (64'b0),
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.mi_dout1 (64'b0),
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.mi_dma_en (),
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/*AUTOINST*/
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// Outputs
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.mi_mmu_en (mi_mmu_en),
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.mi_cfg_en (mi_cfg_en),
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.mi_we (mi_we),
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.mi_addr (mi_addr[14:0]),
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.mi_din (mi_din[63:0]),
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.access_out (etx_cfg_access), // Templated
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.packet_out (etx_cfg_packet[PW-1:0]), // Templated
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// Inputs
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.clk (clk),
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.access_in (etx_access), // Templated
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.packet_in (etx_packet[PW-1:0]), // Templated
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.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), // Templated
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.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), // Templated
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.wait_in (etx_cfg_wait)); // Templated
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/************************************************************/
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/* ETX CONFIGURATION REGISTERS */
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/************************************************************/
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/*etx_cfg AUTO_TEMPLATE (.mi_dout (mi_cfg_dout[DW-1:0]),
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.mi_en (mi_cfg_en),
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);
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*/
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//todo: make more useufl
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assign tx_status[15:0] = 16'b0;
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/*
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{2'b0, //15:14
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etx_rd_wait, //13
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etx_wr_wait, //12
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txrr_fifo_read, //11
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txrr_wait, //10
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txrr_access, //9
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txrd_fifo_read, //8
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txrd_wait, //7
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txrd_access, //6
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txwr_fifo_read, //5
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txwr_wait, //4
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txwr_access, //3
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1'b0, //2
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1'b0, //1
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1'b0 //0
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};
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*/
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etx_cfg etx_cfg (
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_cfg_dout[DW-1:0]), // Templated
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.tx_enable (tx_enable),
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.mmu_enable (mmu_enable),
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.gpio_enable (gpio_enable),
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.remap_enable (remap_enable),
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.gpio_data (gpio_data[8:0]),
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.ctrlmode (ctrlmode[3:0]),
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.ctrlmode_bypass (ctrlmode_bypass),
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// Inputs
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.reset (reset),
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.clk (clk),
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.mi_en (mi_cfg_en), // Templated
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.mi_we (mi_we),
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.mi_addr (mi_addr[RFAW+1:0]),
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.mi_din (mi_din[31:0]),
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.tx_status (tx_status[15:0]));
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/************************************************************/
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/* REMAPPING (SHIFT) DESTINATION ADDRESS */
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/************************************************************/
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/*etx_remap AUTO_TEMPLATE (
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.emesh_\(.*\)_in (etx_\1[]),
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.emesh_\(.*\)_out (etx_remap_\1[]),
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.remap_en (remap_enable),
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.remap_bypass (etx_rr),
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.emesh_wait (etx_wait),
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);
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*/
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etx_remap etx_remap (/*AUTOINST*/
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// Outputs
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.emesh_access_out(etx_remap_access), // Templated
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.emesh_packet_out(etx_remap_packet[PW-1:0]), // Templated
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// Inputs
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.clk (clk),
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.reset (reset),
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.emesh_access_in(etx_access), // Templated
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.emesh_packet_in(etx_packet[PW-1:0]), // Templated
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.remap_en (remap_enable), // Templated
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.remap_bypass (etx_rr), // Templated
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.etx_rd_wait (etx_rd_wait),
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.etx_wr_wait (etx_wr_wait));
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/************************************************************/
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/* EMMU */
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/************************************************************/
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/*emmu AUTO_TEMPLATE (
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.emesh_\(.*\)_in (etx_remap_\1[]),
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.emesh_\(.*\)_out (emmu_\1[]),
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.mmu_en (mmu_enable),
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.mmu_bp (etx_rr),
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.rd_clk (clk),
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.wr_clk (clk),
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.emmu_access_out (emmu_access),
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.emmu_packet_out (emmu_packet[PW-1:0]),
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.mi_dout (mi_mmu_dout[DW-1:0]),
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.emesh_rd_wait (etx_rd_wait),
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.emesh_wr_wait (etx_wr_wait),
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.emesh_packet_hi_out (),
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.mi_en (mi_mmu_en),
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);
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*/
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emmu etx_mmu (
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_mmu_dout[DW-1:0]), // Templated
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.emesh_access_out (emmu_access), // Templated
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.emesh_packet_out (emmu_packet[PW-1:0]), // Templated
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.emesh_packet_hi_out (), // Templated
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// Inputs
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.rd_clk (clk), // Templated
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.wr_clk (clk), // Templated
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.mmu_en (mmu_enable), // Templated
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.mmu_bp (etx_rr), // Templated
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.mi_en (mi_mmu_en), // Templated
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.mi_we (mi_we),
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.mi_addr (mi_addr[14:0]),
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.mi_din (mi_din[DW-1:0]),
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.emesh_access_in (etx_remap_access), // Templated
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.emesh_packet_in (etx_remap_packet[PW-1:0]), // Templated
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.emesh_rd_wait (etx_rd_wait), // Templated
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.emesh_wr_wait (etx_wr_wait)); // Templated
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/************************************************************/
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/*ELINK PROTOCOL LOGIC */
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/************************************************************/
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/*etx_protocol AUTO_TEMPLATE (
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.etx_rd_wait (etx_rd_wait),
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.etx_wr_wait (etx_wr_wait),
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.etx_\(.*\) (emmu_\1[]),
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.etx_wait (etx_wait),
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);
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*/
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defparam etx_protocol.ID=ID;
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etx_protocol etx_protocol (
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/*AUTOINST*/
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// Outputs
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.etx_rd_wait (etx_rd_wait), // Templated
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.etx_wr_wait (etx_wr_wait), // Templated
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.tx_packet (tx_packet[PW-1:0]),
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.tx_access (tx_access),
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.tx_burst (tx_burst),
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// Inputs
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.reset (reset),
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.clk (clk),
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.etx_access (emmu_access), // Templated
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.etx_packet (emmu_packet[PW-1:0]), // Templated
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.tx_enable (tx_enable),
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.gpio_data (gpio_data[8:0]),
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.gpio_enable (gpio_enable),
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.tx_io_wait (tx_io_wait),
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.tx_rd_wait (tx_rd_wait),
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.tx_wr_wait (tx_wr_wait));
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endmodule // elink
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// Local Variables:
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// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl")
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// End:
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/*
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Copyright (C) 2015 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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