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162 lines
2.6 KiB
Markdown
162 lines
2.6 KiB
Markdown
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----
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## How to create a "Hello world" in verilog?
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```verilog
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module hello();
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initial
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begin
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$display ("Hello World!");
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end
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endmodule
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```
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----
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## How to write a verilog testbench?
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EXAMPLE
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----
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## How to run a verilog simulation?
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```
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EXAMPLE
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----
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## How to write a state machine?
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EXAMPLE
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----
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## How to create a synchronous flip-flop?
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```
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always @ (posedge clk)
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if(reset)
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q <= 1'b0;
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else
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q <= d;
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```
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EXAMPLE
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----
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## How to create an asynchronous flip-flop?
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```
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always @ (posedge clk or posedge reset)
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if(reset)
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q <= 1'b0;
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else
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q <= d;
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```
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----
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## How to synchronize a reset across clock domains?
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```
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always @ (posedge tx_lclk_div4 or posedge tx_reset)
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if(tx_reset)
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reset_pipe_lclk_div4b[1:0] <= 2'b00;
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else
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reset_pipe_lclk_div4b[1:0] <= {reset_pipe_lclk_div4b[0],1'b1};
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assign etx_reset = ~reset_pipe_lclk_div4b[1];
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```
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[EXAMPLE](http://github.com/parallella/oh/elink/hdl/etx_clocks.v)
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----
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## How to pass parameters at run time?
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----
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## How to parametrize a module?
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----
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## How to print a number/string with no leading white space?
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```
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$display("%0s\n", mystring);
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```
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----
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## How to check for 'X' in test environments?
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```
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if(fail===1'bX)
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```
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http://www.sutherland-hdl.com/papers/2013-DVCon_In-love-with-my-X_paper.pdf
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----------------------------------------
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## What is the difference between a reg and a wire?
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----------------------------------------
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## How to access hierarchical signals?
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Warning: only works in simulation, not in real designs.
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----------------------------------------
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## How to dump a waveform?
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```
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initial
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begin
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$dumpfile("test.vcd"); //file name to dump into
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$dumpvars(0, top); //dump top level module
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#10000
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$finish; //end simulation
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end
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```
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To dump the waves in .lxt2 format for gtkwave, set the following at the command line.
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```
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setenv IVERILOG_DUMPER lxt2
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----------------------------------------
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## How to initialize a memory from a file?
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```
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initial
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begin
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end
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```
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----------------------------------------
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## How to view a waveform?
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```
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sudo apt-get install gtkwave
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gtkwave test.vcd
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```
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-----------------------------------------
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## How to reduce typing in emacs?
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[Use verilog mode](Use verilog mode)
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-----------------------------------------
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## What are the most important emacs mode keywords?
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* /*AUTOARG*/
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* /*AUTOINST*/
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* /*AUTOWIRE*/
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* /*AUTOINPUT*/
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* /*AUTOOUTPUT*/
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* /*AUTOTEMPLATE*/
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----------------------------------------
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## How do I implement function "X"?
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Single ported memory
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Dual ported memory
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Synchronous FIFO
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Asynchronous FIFO
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Mux2
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Mux4
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Carry Save Adder
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Synchronizer
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Clock divider
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