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87b502ba73
-Making msbfirst the defaualt (looks cleaner on scope) -Swapping bytes on msbfirst and ddr mode -Implementing sdr mode on RX
102 lines
2.8 KiB
Verilog
102 lines
2.8 KiB
Verilog
//#######################################################
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//# Target specific IO logic (fast, timing sensitive)
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//#######################################################
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module mrx_io (/*AUTOARG*/
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// Outputs
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io_access, io_packet,
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// Inputs
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nreset, rx_clk, ddr_mode, lsbfirst, rx_packet, rx_access
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);
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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//parameters
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parameter N = 16;
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//RESET
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input nreset; // async active low reset
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input rx_clk; // clock for IO
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input ddr_mode; // select between sdr/ddr data
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input lsbfirst; // shufle data in msbfirst mode
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//IO interface
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input [N-1:0] rx_packet; // data for IO
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input rx_access; // access signal for IO
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//FIFO interface (core side)
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output io_access; // fifo packet valid
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output [2*N-1:0] io_packet; // fifo packet
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//regs
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reg io_access;
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wire [2*N-1:0] ddr_data;
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reg [2*N-1:0] sdr_data;
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reg byte0_sel;
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//########################################
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//# CLOCK, RESET
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//########################################
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//synchronize reset to rx_clk
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oh_rsync oh_rsync(.nrst_out (io_nreset),
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.clk (rx_clk),
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.nrst_in (nreset)
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);
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//########################################
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//# ACCESS (SDR)
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//########################################
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always @ (posedge rx_clk or negedge io_nreset)
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if(!nreset)
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io_access <= 1'b0;
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else
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io_access <= rx_access;
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//########################################
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//# DATA (DDR)
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//########################################
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oh_iddr #(.DW(N))
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data_iddr(.q1 (ddr_data[N-1:0]),
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.q2 (ddr_data[2*N-1:N]),
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.clk (rx_clk),
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.ce (rx_access),
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.din (rx_packet[N-1:0])
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);
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//########################################
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//# DATA (SDR)
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//########################################
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//select 2nd byte (stall on this signal)
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always @ (posedge rx_clk)
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if(~rx_access)
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byte0_sel <= 1'b1;
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else if (~ddr_mode)
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byte0_sel <= rx_access ^ byte0_sel;
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always @ (posedge rx_clk)
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if(byte0_sel)
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sdr_data[N-1:0] <= rx_packet[N-1:0];
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else
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sdr_data[2*N-1:N] <= rx_packet[N-1:0];
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//########################################
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//# HANDL DDR/SDR
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//########################################
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assign io_packet[2*N-1:0] = ~ddr_mode ? sdr_data[2*N-1:0] :
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ddr_mode & ~lsbfirst ? {ddr_data[N-1:0],
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ddr_data[2*N-1:N]} :
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ddr_data[2*N-1:0];
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endmodule // mrx_io
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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