Andreas Olofsson 8915fd6dfd Adding environment for chip reference model ...

- Turns out I had a nasty bug that was masked by using my own RX to loopback the TX. Since the new RX is very benign with a  programmable fifo full flag the timing is quite relaxed.
- The legacy elink for e16 has a strict wait policy. When wait is raised high, you must stop pretty much immediately.
- I struggled with testing this bug on the parallella for 2 days.
- Putting together the test environment uncovered the bug in a couple of hours. F**K, I should know better!!

2015-11-24 01:07:49 -05:00

..

tests

Adding more test vectors for elink

2015-11-24 01:06:52 -05:00

build_axi_elink.sh

Cleanup

2015-11-09 20:39:48 -05:00

build_eref.sh

Adding environment for chip reference model

2015-11-24 01:07:49 -05:00

build.sh

Cleaning up random dv env

2015-11-17 17:10:57 -05:00

dut_axi_elink.v

Changing testbench to reflect real design

2015-11-18 23:52:10 -05:00

dut_e16ref.v

Adding environment for chip reference model

2015-11-24 01:07:49 -05:00

dut_elink.v

Improving the elink_axi environment

2015-11-18 23:26:59 -05:00

elink_e16_model.v

Moving to MIT license

2015-11-06 11:25:05 -05:00

gen_random.sh

Adding memcpy mode to transaction generator

2015-11-18 23:26:05 -05:00

run_axi.sh

Adding infrastructure for axi_elink

2015-11-03 19:52:08 -05:00

run_eref.sh

Adding environment for chip reference model

2015-11-24 01:07:49 -05:00

run.sh

Initial register test (still debugging)

2015-11-02 19:27:41 -05:00