FPGA/oh

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Andreas Olofsson 8bba86d6cd Adding static phase shif ton RXCLK

-this becomes irrelavent once we have the dynamic idelay on input

2015-10-07 08:57:50 -04:00

common

Changing default to simplify instantiation

2015-05-14 22:46:23 -04:00

edma

Making reset sync in emmu

2015-05-23 22:26:15 -04:00

elink

Adding static phase shif ton RXCLK

2015-10-07 08:57:50 -04:00

emailbox

Fifo cleanup

2015-07-02 16:59:38 -04:00

emesh

Fifo cleanup

2015-07-02 16:59:38 -04:00

emmu

Remving delay from mmu

2015-09-14 13:29:42 -04:00

include

Add ip generation helper script

2015-07-05 19:40:30 +02:00

memory

Writing while full is aserted

2015-08-14 17:15:38 -04:00

parallella/package/xilinx

Adding parallella block design

2015-05-22 21:38:39 -04:00

xilibs

Addding phase delay tracking

2015-09-30 13:40:11 -04:00

.gitignore

Adding register access from RX

2015-04-27 23:51:00 -04:00

configure

Add configure script

2015-07-05 23:30:55 +02:00

CONTRIBUTING.md

Basic infrastructure

2015-04-21 21:36:37 -04:00

COPYING

Basic infrastructure

2015-04-21 21:36:37 -04:00

Makefile.in

Add configure script

2015-07-05 23:30:55 +02:00

README.md

Update README

2015-07-05 23:32:28 +02:00

README.md

=======

OH!

Open Hardware (Pure and Simple)

(work in progress...)

Building

git clone https://github.com/parallella/oh.git
cd oh
mkdir build
cd build
../configure
make elink

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C 5.6%

Shell 0.8%

Python 0.6%

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